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Adventurer
Adventurer
751 Views
Registered: ‎11-07-2012

block design wrapper in systemVerilog

Hi

Is it possible to generate block design wrapper in systemVerilog?

and more specipic - it is possible to make the AXI ports (in or out) as a systemVerilog interface Type for ports of a module?

Tx

Yotam

 

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Moderator
Moderator
703 Views
Registered: ‎04-24-2013

Hi @yotam 

No, not at this time.

When you click on create wrapper it checks what language the project is set to and creates the wrapper based on that.

At this time there are only VHDL or Verilog as options.

Best Regards
Aidan

 

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Adventurer
Adventurer
678 Views
Registered: ‎11-07-2012

thanks

Is system verilog on the Vivado rodemap?

Yoti

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Xilinx Employee
Xilinx Employee
657 Views
Registered: ‎05-22-2018

Hi @yotam ,

There are various features of system verilog which are in roadmap but not sure which one are they. But as per latest Vivado 2019.1 user guide(UG1118) it is recommended to use a Verilog wrapper around a System Verilog file:

wrapperCapture.JPG

Page no. 11 :

https://www.xilinx.com/support/documentation/sw_manuals/xilinx2019_1/ug1118-vivado-creating-packaging-custom-ip.pdf

And we recommend to follow the user guide.

Thanks,

Raj Singh.

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