We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

Showing results for 
Search instead for 
Did you mean: 
Registered: ‎04-28-2014

create_clock problem with OOC module

I have a design which looks roughly like the attached diagram.


Dev A has an MMCM, its being syntheszied and implmeneted in context, and contains a 'create_clock' command for the output of the MMCM.


Dev B uses this clock, and is being created OOC.  It has a constraints file scoped to it, and is set to run out of context only.  In this constraint I issue a create_clock for clk_in.


The problem I am having is after I synthesize and implement the entire design the tools thinks the clock created in Dev A is unique from the clock that is in Dev B.  If I look at the clock interaction report I will see them both listed as timed-unsafe.

0 Kudos
1 Reply
Registered: ‎04-28-2014

Re: create_clock problem with OOC module

It would appear that removing '-name' from the ooc constraints file resolved the issue.  Can someone confirm that this makes sense?

0 Kudos