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jkirby
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Registered: ‎06-07-2011

error when validating board design

I am having difficulty with moving a connection from one slave input to another on the axi_interconnect.

 

The error message is:

WARNING: [IP_Flow 19-4331] Invalid usage of property - Setting errmsg property on PARAM_VALUE.M01_S01_READ_CONNECTIVITY is not allowed in procedure validate_PARAM_VALUE.M01_S01_WRITE_CONNECTIVITY
WARNING: [IP_Flow 19-4331] Invalid usage of property - Setting errmsg property on PARAM_VALUE.M01_S00_READ_CONNECTIVITY is not allowed in procedure validate_PARAM_VALUE.M01_S00_WRITE_CONNECTIVITY
ERROR: [IP_Flow 19-3478] Validation failed for parameter 'My M01_S00_READ_CONNECTIVITY(M01_S00_READ_CONNECTIVITY)' with value '0' for BD Cell 'MicroblazeProc/axi_interconnect_1/xbar'. M01_AXI must be connected to at least one slave interface
ERROR: [IP_Flow 19-3478] Validation failed for parameter 'My M01_S01_READ_CONNECTIVITY(M01_S01_READ_CONNECTIVITY)' with value '0' for BD Cell 'MicroblazeProc/axi_interconnect_1/xbar'. M01_AXI must be connected to at least one slave interface
INFO: [IP_Flow 19-3438] Customization errors found on 'MicroblazeProc/axi_interconnect_1/xbar'. Restoring to previous valid configuration.
ERROR: [Common 17-39] 'set_property' failed due to earlier errors.
ERROR: [BD 41-1273] Error running pre_propagate TCL procedure: ERROR: [Common 17-39] 'set_property' failed due to earlier errors.
    optimize_connectivity_by_mapped_masters Line 199

 

The design has an output from an axi_interconnect master connecting to another axi_interconnect slave (two separate axi_interconnects). The design was working until I removed one of the slave inputs on the second axi_interconnect and moved the above mentioned signal to the open slave port. I then deleted the extra slave input on the second axi_interconnect. This error is now preventing me from validating the design.

 

Has anyone else seen this issue and have a solution?

 

Thanks,

 

JOhn K.

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