how to generate blk ram ip within verilog in vivado?

[ksffj6eu]

Is it possible to generate blk ram ip within verilog using vivado?

i generated one within vhdl,but verilog is requied .How could i config the software tool?

[viviany · Accepted solution]

Check the product buide of the block mem ip you're using to see if this ip provides Verilog language. If it doesn't the only option will be VHDL. If it does, you'll have Verilog source file of the IP as long as you have verilog set as the language in the project settings.

You can use "write_verilog" command to generate the verilog structural model of this IP to use in your project.

1. set the ip as top level

2. run synthesis in out_of_context mode

3. open synthesized design

4. run write_verilog command

Vivian

[bassman59]

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@ksffj6eu wrote:

Is it possible to generate blk ram ip within verilog using vivado?

i generated one within vhdl,but verilog is requied .How could i config the software tool?

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You should probably infer the memory rather than generating an IP core.