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Explorer
Explorer
180 Views
Registered: ‎10-09-2017

how to read in AXI4-Lite Master for User IP

I have made an  AXI4-Lite Master for User IP, but I don't know the read logic.

I want to read with address in32 and output with out32.

I also found the explain in my file AzIP_AXI_Master_v1_0_M00_AXI.v

//------------------
//Read example
//------------------

//Terminal Read Count

always @(posedge M_AXI_ACLK)
begin
if (M_AXI_ARESETN == 0 || init_txn_pulse == 1'b1)
last_read <= 1'b0;

//The last read should be associated with a read address ready response
else if ((read_index == C_M_TRANSACTIONS_NUM) && (M_AXI_ARREADY) )
last_read <= 1'b1;
else
last_read <= last_read;
end

/*
Check for last read completion.

This logic is to qualify the last read count with the final read
response/data.
*/
always @(posedge M_AXI_ACLK)
begin
if (M_AXI_ARESETN == 0 || init_txn_pulse == 1'b1)
reads_done <= 1'b0;

//The reads_done should be associated with a read ready response
else if (last_read && M_AXI_RVALID && axi_rready)
reads_done <= 1'b1;
else
reads_done <= reads_done;
end

 

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Moderator
Moderator
123 Views
Registered: ‎11-09-2015

Re: how to read in AXI4-Lite Master for User IP

HI @liwenz 

You can create a new package IP with AXI peripherals in vivado (Tools > Create an package new IP > Create a new AXI4 Peripheral). This will generate template for the AXI4 interfaces


Florent
Product Application Engineer - Xilinx Technical Support EMEA
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