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Contributor
Contributor
572 Views
Registered: ‎02-23-2014

ip integrator gui problem

 

vivado 2017.4

 

I have 4 Ethernet ports inside a hierarchical block, at every compilation of my design I need to delete the outer and inner connections and ports or else there would be errors regarding the bus directions (out get connected to out and in get connected to in)

 

My initial post (before I understood the real cause)

https://forums.xilinx.com/t5/Embedded-Processor-System-Design/mdio-zynq-error/td-p/847270

 

steps that I tried:

1. only delete the outer connections

2. only delete the inner connections (ports was not deleted)

 

 

any ideas?

Hanan

 

 

ipi gui.JPG
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Xilinx Employee
Xilinx Employee
504 Views
Registered: ‎07-22-2008

Re: ip integrator gui problem

This is not a known problem that I could find.

How are the interfaces connected inside the Ethernet hierarchy?  Are they connected to Xilinx IP, user IP, HDL reference modules?

 

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