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Participant deritha-06
Participant
8,151 Views
Registered: ‎04-15-2010

map error?

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There are 8 errors when I tried to run map in Implement Design.

 

Problem is that I don't know where to modify these errors?

 

Please tell me if you have any suggestion.

 

Thanks

map-problem.PNG
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1 Solution

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Participant deritha-06
Participant
9,897 Views
Registered: ‎04-15-2010

Re: map error?

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Please ignore the error message about time_cnt.vf. I've fixed it.

 

I also understand why there are errors in map process. I should edit the scf file firstly............

 

Thanks.

View solution in original post

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7 Replies
Instructor
Instructor
8,144 Views
Registered: ‎08-14-2007

Re: map error?

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Your project is expecting to build for a part in a VQ100 package, which has pin numbers

like 1, 2, 3, 4, 5, ..., 100.  These can alternately be called "P1", "P2", "P3", . . . "P100" for

the location constraint.

 

However it looks like your .ucf file has pin constraints for a BGA package.  If the .ucf file is

correct for your board, then you need to change the device selection in the project properties.

 

HTH,

Gabor

-- Gabor
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Participant deritha-06
Participant
8,145 Views
Registered: ‎04-15-2010

Re: map error?

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Thanks.

 

The .ucf file is generated by : Project-> New Source, select Implementation Constraints File-> Type stopwatch.ucf.....

 

The board I'm using now is SPARTAN-3E XC3S500E

 

The attachment shows the information in Design Properties.

 

I still don't know what I could do to fix the bugs.....

property.PNG
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Historian
Historian
8,126 Views
Registered: ‎02-25-2008

Re: map error?

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So change the Device and Package to whatever is correct for your FPGA!
----------------------------Yes, I do this for a living.
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Advisor eilert
Advisor
8,100 Views
Registered: ‎08-14-2007

Re: map error?

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Hi,

minor correction:

 

Not the device selection has to be changed,

but the Package Selection.

 

See if your UCF file contains some information (e.g. in a comment) about the Device and Package it was written for.

At least it has to be some kind of 2D-Pin Array (PGA or BGA Package).

 

Have a nice synthesis

  Eilert

 

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Participant deritha-06
Participant
8,090 Views
Registered: ‎04-15-2010

Re: map error?

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Thanks all of you for your kind reply.

 

It's because I'm fresh about this part, so many different error messages output.

 

As to the UCF file, I just checked out from the xilinx tutorial webpage.

 

I design the software part names vtut_ver as the ise11tut.pdf's introduce.

 

The problem is I don't know how to connect the spartan-3e board and the vtut_ver software.

 

Only one usb cable is enough to connect with board and computer?

 

One more question: "time_cnt.vf" line 23 Illegal redeclaration of 'time_cnt'. I didn't find any redeclaration of clr in this file. What's more, this file is the standard checked out file........

 

 

time_cnt.PNG
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Participant deritha-06
Participant
9,898 Views
Registered: ‎04-15-2010

Re: map error?

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Please ignore the error message about time_cnt.vf. I've fixed it.

 

I also understand why there are errors in map process. I should edit the scf file firstly............

 

Thanks.

View solution in original post

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Moderator
Moderator
8,013 Views
Registered: ‎02-07-2008

Re: map error?

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MAP/PAR related topics should be posted on the Implementation forum:

 

http://forums.xilinx.com/t5/Implementation/bd-p/IMPBD

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