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jeloyah
Visitor
Visitor
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Registered: ‎10-20-2017

"[DRC INBB-3] Black Box Instances." Unable to instantiate user created IP's

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I've created some IP, according to the UG118 Creating and Packaging Custom IP

When I try to instantiate them (in a new project), I received these messages:

"[DRC INBB-3] Black Box Instances: Cell 'xx' of type 'xxxxxxx' has undefined contents and is considered a black box. The contents of this cell must be defined for opt_design to complete successfully."

 

I found some similar messages in the forum, but none of the solutions worked for me. 

 

What I'm doing wrong?

(Using Win 10 Pro, 64b & Vivado 2017-2)

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florentw
Moderator
Moderator
20,801 Views
Registered: ‎11-09-2015

Hi @jeloyah,

 

Sorry about the delay. There is a mismatch between the name of your IPs as they have been added to the project and the name you are using to instantiate them to your project.

 

Basically, when you add an IP to you project, you select an name which is not necessarily the "catalog name of the IP". By default, it is not. Vivado add an index to the name. This way you could add multiple time the same IP but with different configurations.

 

If you modify your top level vhdl file, your issue will be solved (I have attached a corrected version).

 

Hope that helps,

 

Regards,

 

Florent


Florent
Product Application Engineer - Xilinx Technical Support EMEA
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View solution in original post

14 Replies
hpoetzl
Voyager
Voyager
18,494 Views
Registered: ‎06-24-2013

Hey @jeloyah,

 

Make sure the IP is available to the new project (i.e. in the IP path).

Maybe provide a minimal example which shows your problem.

 

Best,

Herbert

-------------- Yes, I do this for fun!
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jeloyah
Visitor
Visitor
18,476 Views
Registered: ‎10-20-2017

@hpoetzl

1) I made a bin to bcd converter (created the project, entered the VHDL code, synthesized it and generated the IP). Everything was OK.

2) I created some other VHDL files, synthesized them, and generated the IP's. Everything was OK.

3) Then I created a top-level project where I defined the new repository. Next I instantiated the IP created before and mapped them (PORT MAP). Everything sinthesized fine.

4) When I tried to implement this top-level project, I received the message [DRC INBB-3] Black Box Instances: Cell 'xx' of type 'xxxxxxx' has undefined contents and is considered a black box. The contents of this cell must be defined for opt_design to complete successfully.

 

 According to Xilinx documentation, the IP can be in a different directory than the project which instantiates it. In fact, I see in the project's folder (/xxxxx_user_files/ip) some subfolders with info about the IP's instantiated (I suppose these folders were created by Vivado; I didn't created them).

 

   What do you mean by "IP is available to the new project (in the IP path)" ?

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florentw
Moderator
Moderator
18,466 Views
Registered: ‎11-09-2015

Hi @jeloyah,

 

When creating a new project, you need to add you IP directory to the IP repo path:

repo.PNG

 

Hope that helps,

 

Regards,

 

Florent


Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**
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jeloyah
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Registered: ‎10-20-2017

@florentw

Yes, the IP's directories are already in the IP repo path (I specified the repository when I called IP catalog, then added every IP I'm going to map inside the project).

 

Anyway, this doesn't seem to be the issue, since Vivado is synthesizing the design OK.

 

Synthesis is fine, port mapping is fine, the IP's were synthesized/implemented OK, the IP route is OK. Just the Implementation is throwing the "DRC INBB-3 message error".

 

How is this possible? 

Is there another alternative for instantiate / use those IPs?

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florentw
Moderator
Moderator
18,451 Views
Registered: ‎11-09-2015

HI @jeloyah,

 

Could you share your project? I can have a look.

 

Regards,

 

Florent


Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**
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jeloyah
Visitor
Visitor
18,442 Views
Registered: ‎10-20-2017

@florentw
This is the project where I'm pretending to use IP:s

 

modules to be created as IPs:

bin_to_bcd_4b
bin_to_bcd_6b
contador_seg_min_hrs
hex_to_sseg_K

 

IPs created:

ip_bin_to_bcd_4b
ip_bin_to_bcd_6b
ip_contador_seg_min_hrs
ip_hex_to_sseg_K

 

top level project where IPs are instantiated:

reloj_s_m_h

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florentw
Moderator
Moderator
20,802 Views
Registered: ‎11-09-2015

Hi @jeloyah,

 

Sorry about the delay. There is a mismatch between the name of your IPs as they have been added to the project and the name you are using to instantiate them to your project.

 

Basically, when you add an IP to you project, you select an name which is not necessarily the "catalog name of the IP". By default, it is not. Vivado add an index to the name. This way you could add multiple time the same IP but with different configurations.

 

If you modify your top level vhdl file, your issue will be solved (I have attached a corrected version).

 

Hope that helps,

 

Regards,

 

Florent


Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**

View solution in original post

jeloyah
Visitor
Visitor
18,418 Views
Registered: ‎10-20-2017

@florentw

 

It works! 

 

When I was trying to solve this issue, once, I thought about the mismatch but never tested if this could be the problem. Your explanation sounds reasonable, but I don't remember if any part of the documentation prevents about this situation.

 

Thanks a lot for your invaluable time, your patience and your effort.

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florentw
Moderator
Moderator
18,412 Views
Registered: ‎11-09-2015

Hi @jeloyah,

 

I don't remember if any part of the documentation prevents about this situation.

> This is more a coding issue. We cannot document every issue...


Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**
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15,294 Views
Registered: ‎07-17-2018

Hello,

 

I know the topic is closed but I encoutered the same issue and this solution did not help me solving the problem.

It turns out that my problem came from the packaging of a custom in the first place. I repackaged the concerned IP (after generating the output products, I had not done it before) and it worked !

 

Hope that will help others,

 

Yannick

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florentw
Moderator
Moderator
15,281 Views
Registered: ‎11-09-2015

Hi @yannick_molinghen,

 

You might want to create a new topic for your issue rater than replying on an old topic.

 

In your new topic, please make sure to detail your issue, the vivado version and share a test case if possible.

 

Regards,


Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**
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praseetha
Visitor
Visitor
2,965 Views
Registered: ‎02-05-2021

blackbox.PNG

Hello @hpoetzl,

I am also facing the same issue in vivdo 2020.2 . I did not get any error during sythesis but only this warning and later during implementation I could not implement it due to this error. I also added the IP path to the design repositary. 

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praseetha
Visitor
Visitor
2,962 Views
Registered: ‎02-05-2021

path.PNG

This is the name of module and I have not created any Pl yet.

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Nagi_M
Visitor
Visitor
2,214 Views
Registered: ‎03-09-2021

hello @jeloyah  how did you solve the problem, am also facing the same issue after changing the IP names. Can you please help me to sort it out ?

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