11-12-2018 01:53 PM
I'd like to use a PS gtr_ref_clk as the source for a Zynq PL clock. According to UG1085 v1.8 pages 1100 to 1101 this should be possible. My question is how can I configure the Zynq IP block in my Vivado design to actually do this?
11-12-2018 06:31 PM
11-13-2018 06:56 AM
Unfortunately this does not answer my question. I already have a design that uses PS PLL's to drive PL side clocks. I understand the basic concept of that just fine. My question is very specifically about what I need to alter in the Zynq IP block itself in the block design in order to generate an HDF & FSBL that represents my intention of routing the gtr_ref_clk to the RPLL for use in PL clock generation?
I provided the diagram because it indicates that the MUXing inside the PS is designed to support this, but again how do I create the hardware design so that it will translate into utilizing the gtr_ref_clk to run the RPLL?
11-13-2018 07:03 AM
You see how I can choose the source for the RPLL, but it only shows options for PSS REF CLK and PSS ALT REF CLK, where are the other options??
11-27-2018 09:34 AM
@rshekhaw Any other advice you can provide on how to use the tool to accomplish this? Perhaps this feature isn't fully implemented and an SR for Vivado enhancement is required? Would just like to know best path forward here please.