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Registered: ‎06-17-2019

spartan7 power wiring (LVDS 25)

I want to use LVDS communication with spartan7

 

Do you have to set the power separately except Vccint, Vccaux, VccBram, Vcco, Vccbatt?

 

Currently, VCCint 1V, Vccaux 1.8V, VccBram 1V, Vcco 3.3V, Vccbatt 1.8V will be applied.

 

 

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Registered: ‎01-22-2015

@kjh741kj 

Welcome to the Xilinx Forum!

     Currently, VCCint 1V, Vccaux 1.8V, VccBram 1V, Vcco 3.3V, Vccbatt 1.8V will be applied.
These are recommended voltages for -2 and -1 grade per Table 2 of Xilinx document DS189.  These voltages should be applied to the Spartan-7 per the “Power-On/Off Power Supply Sequencing” shown on page 7 of DS189(v1.9).

     I want to use LVDS communication with spartan7
In short, it’s all about matching specifications for (VIDIFF, VICM) at the receiver with specifications for (VODIFF, VOCM) at the transmitter - and ensuring that an external LVDS transmitter is not sending signals that can damage the FPGA (ie. that exceed Absolute Maximum Ratings shown in the FPGA datasheet).

Per Table 1-7 of Xilinx document UG475, the Spartan-7 has only HR-type banks of IO.  Per Table 1-43 of UG471, LVDS is available only in Vcco=1.8V HP-type banks.  So, the Spartan-7 cannot directly use LVDS.  However, Table 1-7 of UG475 shows that the Spartan-7 HR banks can use LVDS_25.  The specifications for (VIDIFF, VICM, VODIFF, VOCM) of LVDS_25 are shown in Table 11 of DS189.  However, to use LVDS_25, you need to change Vcco from 3.3V to 2.5V.

Also, as described on page-92 of UG471(v1.10), you might be able to receive LVDS using LVDS_25.

Please also read AR40191 and AR43989 As described in AR43989, the old LVDS_33 standard is not supported by the 7-Series FPGAs.

Cheers,
Mark

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