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Visitor aeley
Registered: ‎03-10-2010

two rank DDR3 controller

I'm designing a board with a virtex6 and descrete DDR3 components (no DIMMs), and I would like to have a 533MHz x32 DDR3 controller that supports 2 ranks. There are no options in MIG for adding a rank with discrete parts, but is seems the controller files have the parameters for multiple ranks. Aside from adding the additional 5 lines/pins (CK,CK#,CS,CKE,ODT) to the .ucf file, which parameters do I need to edit to add a rank and how can I make sure it maps?

Will a second rank even work for a x32 interface?

Since I'm using discrete DDR3 parts on the same PCB near the FPGA, do I really need extra CK,CK#,CKE, and ODT lines, or would having them be easier anyway since that's how the controller is organized?



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Xilinx Employee
Xilinx Employee
Registered: ‎10-23-2007

Re: two rank DDR3 controller

This design will only calibrate on one rank.  Thus it is recommended only for lower frequencies.  If you know that the ranks will be very well matched for timing, then you may be able to run faster, but you need to do your own characterization of this.  You should do an SI analysis with the additional loading you mention.  533 MHz is the upper limit for the single rank design.  I would not recommend attempting this speed with dual rank.
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