UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

cancel
Showing results for 
Search instead for 
Did you mean: 
Visitor sam91
Visitor
8,549 Views
Registered: ‎09-08-2012

AES encryption using Verilog

So I took it upon myself to learn all about the FPGA this semester. To test my skills, I picked up a project to encrypt and decrypt files using a FPGA implementation of the age old AES. Now implementation of AES using Verilog has been done umpteen times and for my reference I used the code at http://opencores.org/project,systemcaes. What I wish to do is use the Verilog file handling functions to read a small file, use it as input to the encryption block on the FPGA, and save the encrypted file back on the computer. I am aware that this can be done on the testbench(though I have not attempted it, I am sure it can be done). But how do I do the same when I implement the code on the FPGA board? Is there a way to select the file to be encrypted/decrypted and pass it onto the board? Is it even possible?

 

I read somewhere tha tVerilog RTL does not have a concept of a file system, you would need the FPGA 'driver' to break the file down and send it over byte by byte or load it into a memory for the program on the FPGA to read. But what exactly is this 'driver' that they speak of? And how would I use it to break the file down without using the Verilog R/W commands and load it into the memory? Sorry if I am asking too many questions and come across as a newbie, I am just new to the FPGA world.

 

Thanks in advance everyone.

0 Kudos
8 Replies
Historian
Historian
8,536 Views
Registered: ‎02-25-2008

Re: AES encryption using Verilog


@sam91 wrote:

I read somewhere tha tVerilog RTL does not have a concept of a file system,


Verilog does have rudimentary file I/O support, however, if the code is to be synthesized you can't use that feature.

 

Ask yourself why that would be the case.


you would need the FPGA 'driver' to break the file down and send it over byte by byte or load it into a memory for the program on the FPGA to read. But what exactly is this 'driver' that they speak of? And how would I use it to break the file down without using the Verilog R/W commands and load it into the memory? Sorry if I am asking too many questions and come across as a newbie, I am just new to the FPGA world.


"Driver" is likely the wrong word and it's possible that the article you read was written by a software person who really had no business discussing hardware design.

Anyway, what you need to do is work out a mechanism to get the unencrypted data from the computer (I assume it's on a computer) to the FPGA and then send the encrypted data back to the computer.

That transport, as they say, is an exercise left to the reader. You could do it over standard RS-232 UART, or over Ethernet, or over USB, or over FireWire, or perhaps using some wireless mechanism, you name it. It all depends on what you want to build.

----------------------------Yes, I do this for a living.
Visitor sam91
Visitor
8,532 Views
Registered: ‎09-08-2012

Re: AES encryption using Verilog

Thanks for the prompt reply bassman59.

My target device is a Diligent Spartan 3E board, which does have RS-232 as well as USB support. So the means of the transport are taken care of. But how exactly will I transport the file from the PC? Do I have to write some code for that? And yes, the code is to be synthesized so I supposed Verilog file handling is out of the picture. Some resources would be helpful. So far I could only find how to configure the board using USB, but I could never find how to transfer a file using USB...

Thanks in advance yet again. This forum is amazingly helpful.

0 Kudos
Historian
Historian
8,523 Views
Registered: ‎02-25-2008

Re: AES encryption using Verilog


@sam91 wrote:

Thanks for the prompt reply bassman59.

My target device is a Diligent Spartan 3E board, which does have RS-232 as well as USB support. So the means of the transport are taken care of. But how exactly will I transport the file from the PC? Do I have to write some code for that?


That's entirely up to you. Many people have written little programs which read files from a hard disk and send the contents over an RS-232 link. Or you could use a terminal emulator to do that for you. You could use XMODEM or another standard protocol. There are many options.


And yes, the code is to be synthesized so I supposed Verilog file handling is out of the picture. Some resources would be helpful. So far I could only find how to configure the board using USB, but I could never find how to transfer a file using USB...


Configuring the FPGA is an issue that's entirely separate from sending arbitrary user data to and from the FPGA.

 

The fact that the FPGA can be configured over USB is a detail, in that in the case of your board, the equivalent of the standard Xilinx JTAG dongle (which talks to the computer over USB, but older models used RS232 or Centronics-parallel) is embedded in the board. That USB port talks only to the JTAG chain. You could easily program the board's configuration EPROM over JTAG (via USB) and when you cycle power on the board, it boots your code from the EEPROM. Point, though, is that the configuration JTAG port is unavailable for use as a general-use USB port.

 

(And really, there's no such thing as a "generic USB port." USB "ports" are enumerated by the host computer as a "device" that conforms to a specific "device class.")

 

So if you are left with only the RS-232 serial port as the interface to the host computer, start there. How you handle the data transfer is entirely up to you. There are no standards other than the signaling over the wire itself.

 

Your board has plenty of SRAM so using it as a buffer for XMODEM-1K is reasonable.

----------------------------Yes, I do this for a living.
0 Kudos
Visitor sam91
Visitor
8,505 Views
Registered: ‎09-08-2012

Re: AES encryption using Verilog

Thank you bassman59 for you solutions. They have been very helpful and knowledgeable.

 

For the record, I do know the difference between configuring a FPGA device and sending arbitrary user data to it. I have tested my skills using simple programs such as counters, adders etc and implementing them on the FPGA. But that the USB port is not a generic one and can not be used to transfer data is something that I did not know. So a big thanks for that.

 

After a little reading I think I will give the opensource TeraTerm a try. Thanks for all your help once again. Really, can't thank you enough. But am afraid to say that I will have some other queries as I proceed, and I will have to rely on this excellent forum with members like you to help me out.

 

Kudos.

0 Kudos
Explorer
Explorer
8,487 Views
Registered: ‎12-31-2012

Re: AES encryption using Verilog

XMODEM brinks back some old memories... file transfers over FIDO net on a Hayes 9600.
---------------------------------------------------------------------------------
I like these books:
Free Range VHDL (free), http://www.freerangefactory.org/site/pmwiki.php/Main/Books
VHDL for Logic Synthesis, Andrew Rushton
FPGA Prototyping by VHDL Examples, Pong P Chu
0 Kudos
Historian
Historian
8,472 Views
Registered: ‎02-25-2008

Re: AES encryption using Verilog


@sam91 wrote:

 

After a little reading I think I will give the opensource TeraTerm a try. Thanks for all your help once again. Really, can't thank you enough. But am afraid to say that I will have some other queries as I proceed, and I will have to rely on this excellent forum with members like you to help me out.

 

Kudos.


TeraTerm is pretty good. I use it all the time; one of the features that's quite useful is its XMODEM (and YMODEM and ZMODEM) transfer capability.

----------------------------Yes, I do this for a living.
0 Kudos
Visitor mahimagoyen
Visitor
1,110 Views
Registered: ‎10-29-2018

Re: AES encryption using Verilog

Hey, can you please send me the code on my email id. I need the code urgently but the website(opencores) will activate my account in 1-2 days. Please help me.

mahimagoyen1996@gmail.com

0 Kudos
106 Views
Registered: ‎10-07-2019

Re: AES encryption using Verilog

Hi, 

If you have the AES verilog code can you help me and send it to my email malaaeddin@sharjah.ac.ae. Also if you can help to teach me how to run the code in FPGA Board. Thanks 

0 Kudos