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Registered: ‎01-11-2015

Automating Top Level Wrapper

I have posted recently about tri-state buffers in BD design and wanted to follow up with the question of whether people have encountered modifying the Top Level design file, and then lose that work when regenerating the BD design?

Depending on how much Verilog and work effort was put into modifying the BD design, this could be quite a time issue. So what I decided to do is implement as basic of automation process as possible with respect to the top level file. In this case, about 20 lines of Python...

Every time I regenerate the BD design, the top level wrapper is updated. I simply run the Python and insert all the tri-state logic there. It would be nice if Vivado had the ability to call into a automatic function after generating the top level wrapper. For example, when using Vivado to make an AXI peripheral IP, there is a section of the Verilog code for the user to enter their logic. I am thinking the same thing for the Top Level Wrapper, and some mechanism to call into auto generatin of code.

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