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Contributor
Contributor
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Registered: ‎10-16-2017

Benchmarking FSMs and strategies.

I want to benchmark some aspects of the FSM coding and Vivado synthesis/implementation strategies. I am going to use FSMs from the MCNC benchmark. I already have the overall idea, however there are some aspects, that I am not sure about and I would be really grateful if you could give me some advices.

1. As there there are 56 FSMs in the MCNC benchmark, at least 6 FSM codings that I want to check, and at least 4 different strategies combinations that I want to check, there will be at least 1344 cases that I will need to run synthesis and implementation for. It is obvious, that it needs automation. Fortunately I have it already done, but there is one thing that I want to compare in my benchmark, that I am not capable to fetch from files, namely design runs times, that are displayed in the Vivado in GUI mode:

design_runs.png

Does anyone how to fetch Elapsed times from files generated by Vivado. These values are probably sums of the times available in the files in the project.runs directory. I have grepped these files for given values, but without success, that is why I assume this Elapsed time is split into different phases in the files under .runs directory.

 

2. One of the things that I want to benchmark is the average maximum possible frequency for given FSM/strategy. Here is how I want to approach this aspect. I want to benchmark for one of the Artix parts with the lowest amount of logic resources and the slowest speed grade. I plan to create single clock, with the frequency such that all FSMs will implement without timing violations, however not too small. Something between 200-300 MHz. Then I want to estimate maximum frequency based on the Worst Negative Slack: f_max = 1 / (created_clock_period - WNS) * 10^6. I have already realized, that the higher is the frequency of the created clock the more accurate is the estimation. What do you think about this approach?

 

3. FSMs from the benchmark have different number of inputs and outputs. I would like to run synthesis and implementation for each of them without defining clk, input and output pins locations in the .xdc (only with single create_clk for clk port). I wonder, if this can have any significant impact on the results?

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3 Replies
Scholar drjohnsmith
Scholar
237 Views
Registered: ‎07-09-2009

Re: Benchmarking FSMs and strategies.

I dont know what your trying to achieve , but a few observations,

 

Those benchmarks are very small, the amount of logic and registeres used is minimal.

    As such, the computer its running on has considerable effect upon the implimentaiton numbers.

  Whats more ,

    Im guessing your using the web pack, so its "calling home". So the speed and latency of your network and web connection will also vary run to run, and will not only be a big part of the small run time, but also a variable part.

 

Its also important to remember that vivado runs till it meets your timming constraints.

     As soon as the run meets the constraint, it will stop. This is unlikely to be the fastes the design can run. Also if you over constrain, then the tools can end up getting "blocked" during routing and come up with a worse time than wiht a slighty slower time constraint, ...

Also rember, you computer is not runnig the single Vivaod job,

   My computer here for instance says it has over 100 tasks running, taking lumps of the system at various times.

          this veriability you will have to take account off.  I dont know how... 

 

All in all, I doubt you will get much if any useful information, and will get lots of missleading answers.

 

If you want to learn good coding styles, 

   best bet is to look in "good books" and copy styles,

 

( dont look at the xilinx examples built into vivado , they are 30 odd years out of date )

  

 

 

<== If this was helpful, please feel free to give Kudos, and close if it answers your question ==>
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Contributor
Contributor
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Registered: ‎10-16-2017

Re: Benchmarking FSMs and strategies.


@drjohnsmith wrote:

I dont know what your trying to achieve , but a few observations,

 

Those benchmarks are very small, the amount of logic and registeres used is minimal.

    As such, the computer its running on has considerable effect upon the implimentaiton numbers.


Yes, that is why I am not going to compare some of the results (such as run times) generated by different machines.

 


  Whats more ,

    Im guessing your using the web pack, so its "calling home". So the speed and latency of your network and web connection will also vary run to run, and will not only be a big part of the small run time, but also a variable part.


This guess is wrong.

 


Its also important to remember that vivado runs till it meets your timming constraints.

     As soon as the run meets the constraint, it will stop. This is unlikely to be the fastes the design can run. Also if you over constrain, then the tools can end up getting "blocked" during routing and come up with a worse time than wiht a slighty slower time constraint, ...


That is why I want the initially created clock frequency to be as high as possible, but not too high so that all FSMs can implement without timing constraints. The estimated max frequencies will be more accurate then.



Also rember, you computer is not runnig the single Vivaod job,

   My computer here for instance says it has over 100 tasks running, taking lumps of the system at various times.

          this veriability you will have to take account off.  I dont know how... 


This is true, but with 56 FSMs per configuration this should have roughly the same effect on each scenario. As I will compare results relatively, and all of them will be generated on the same machine I think this effect can be neglected.

 


All in all, I doubt you will get much if any useful information, and will get lots of missleading answers.


 I have already spotted few interesting things running a bunch of tests by hand. Actually this is the reason why I decided to dig further.

 

If you want to learn good coding styles, 

   best bet is to look in "good books" and copy styles,

 

( dont look at the xilinx examples built into vivado , they are 30 odd years out of date )


If I take into the consideration all aspects of FSM coding, I think I would be able to write the same FSM in 40-50 different ways.

I have choosen few of them, that are common or interesting, that I want to benchmark. I am just saying 'check'.

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Scholar drjohnsmith
Scholar
203 Views
Registered: ‎07-09-2009

Re: Benchmarking FSMs and strategies.

good luck
it will be interesting to see your results published and peer reviewed.
<== If this was helpful, please feel free to give Kudos, and close if it answers your question ==>
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