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Explorer
Explorer
952 Views
Registered: ‎11-05-2008

Custom IP block in a black box design

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We have a project, for a Zynq Ultrascale+ device, in which a small part of the design could be opened for custom development: this custom block can be seen as

a IP with a standardized interface (axi stream input/outputs; axi-lite for register access). The other part of the design should be a black box for end user.

It could be a "grey" box if one could use intermediate formats for sharing (such as netlist of DCP).

What is the recommended flow to handle such a design?

Thanks,

Luca

 

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Xilinx Employee
Xilinx Employee
923 Views
Registered: ‎11-17-2008

Re: Custom IP block in a black box design

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@colombini_luca

The Partial Reconfiguration design flow can help meet these needs, even if dynamic reconfiguration is not a requirement.  The PR flow allows you lock down parts of the design (the "static" and any current modules tagged as reconfigurable), keep modules empty during implementation (the "grey box" you note) and ultimately focus on one part of a design at a time, for a single designer or multiple users.  Appendix A of UG909 has details on the in-context Hierarchical Design use case, and the doc overall covers the PR solution.

Yes, a design checkpoint (DCP) is the file needed for one user to share the static design database with another user for them to insert their code, replacing the grey/black box.  This module implementation is done in context with the locked top level, so the entire static design is shared in this checkpoint.  Other Reconfigurable Partitions could be used for "secret" information -- remove this logic, replacing it with a grey box.  We are also developing a solution to be released next year that removes much of the static design, hiding this information from the end user.  Send me a PM with more of your design details and background if you'd like to know more about this last approach.

thanks,

david.

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Xilinx Employee
Xilinx Employee
924 Views
Registered: ‎11-17-2008

Re: Custom IP block in a black box design

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@colombini_luca

The Partial Reconfiguration design flow can help meet these needs, even if dynamic reconfiguration is not a requirement.  The PR flow allows you lock down parts of the design (the "static" and any current modules tagged as reconfigurable), keep modules empty during implementation (the "grey box" you note) and ultimately focus on one part of a design at a time, for a single designer or multiple users.  Appendix A of UG909 has details on the in-context Hierarchical Design use case, and the doc overall covers the PR solution.

Yes, a design checkpoint (DCP) is the file needed for one user to share the static design database with another user for them to insert their code, replacing the grey/black box.  This module implementation is done in context with the locked top level, so the entire static design is shared in this checkpoint.  Other Reconfigurable Partitions could be used for "secret" information -- remove this logic, replacing it with a grey box.  We are also developing a solution to be released next year that removes much of the static design, hiding this information from the end user.  Send me a PM with more of your design details and background if you'd like to know more about this last approach.

thanks,

david.

Explorer
Explorer
906 Views
Registered: ‎11-05-2008

Re: Custom IP block in a black box design

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Thanks @davidd.

If I have a design with a VHDL top level that instantiate a user logic block (pure VHDL) and than a block diagram (via wrapper),

should I be able to get the DCP from the block diagram and use it in another project with the same architecture (user block + CDP)?

I will make a try asap, but I would like to have your opinion.

Luca

 

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Explorer
Explorer
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Registered: ‎11-05-2008

Re: Custom IP block in a black box design

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Hi @davidd, how can I send you a PM?

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Xilinx Employee
Xilinx Employee
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Registered: ‎11-17-2008

Re: Custom IP block in a black box design

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@colombini_luca,

Just click on my name and you see my profile.  On that page you can see the "send this user a private message" button.

 

Yes, you'd be able to use a DCP from a block diagram in any design, as you can simply treat it like a netlist.  Once it has been synthesized out-of-context, that netlist can be inserted in any design that targets the same device.  This would most easily be done in a non-project scripted flow where you simply link in that checkpoint.

* If you bring the DCP into a new project, it will be uniquified for that project and live separately from the original.  That would be an option if you want to make changes to the DCP.  But then it would need to be exported as a DCP (after synthesis with the wrapper VHDL top) as we do not yet support block diagrams in RMs in project mode.

** All this reuse of BDs and DCPs are at the post-synthesis level, not post-route.  Place and route of these modules must be done in context with the top level (static) design, which would be different in these cases.

thanks,

david.

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