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1,234 Views
Registered: ‎06-08-2018

Different partial bit streams for one partial reconfigurable partition

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Dear all

Due to this fact that, at any given point of time, each dynamic partition of the FPGA consists of some modules that are plugged in and reconfigured on the fly. These modules may have varying requirements of I/O connection, and we must assume the worst case and anticipate these requirements, so every partition must have all the connections that its modules may need before.

 

for example, partition definition in top module (as a black box )is like this :

module recon_block_count(
input clk,
input rst_n,

input test,
output [3:0] out_counter)

and we connect some of this input/outputs to I/Os.

 

 

and we wanna place a bitstream in this partition which doesn't have one of input pins in its netlist at all.

Is there any way to assign a bit stream that is generated from the following module which doesn't have " input test" to this partition?

module recon_block_count (
clk,

rst_n,
out_counter);

 

or all the bitstream must have same definition in module? 

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Moderator
Moderator
1,353 Views
Registered: ‎11-04-2010

Re: Different partial bit streams for one partial reconfigurable partition

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Hi, @hanieh_jafarzadeh ,

It looks that your customer and you are working as team-design. Please consider the below points:

1. What your customer and you should decide:

   <1> All the possible ports required in all the RMs of RP.

   <2> The pblock for RP in the design.

2. You should send your new static synth dcp and top constraints to your customer if you change anything in the static part.

3. Your customer should run implement for his RM with your latest static design. 

4. Since the design will be reconfigured remotely, you have to create decouple logic to avoid data corruption during reconfiguration.

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5 Replies
Moderator
Moderator
1,224 Views
Registered: ‎11-04-2010

Re: Different partial bit streams for one partial reconfigurable partition

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Hi, @hanieh_jafarzadeh ,

All the bitstreams must have same definition in module.

In some Reconfigurable Modules (RM) of the Reconfigurable Partition (RP), some input ports will be unused, but all the ports of RP should be seen for top level.

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1,214 Views
Registered: ‎06-08-2018

Re: Different partial bit streams for one partial reconfigurable partition

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Dear @hongh

thanks for your reply 

I have a FPGA that place some designs on its static part and my customers can remotely send their partial bitstreams through an Ethernet connection into my reconfigurable partitions. 

so according to what you say, I must tell them that they must send their bit streams in a uniform manner 

I think it's a limitation to use FPGAs.

do you have any suggestions to implement such a design that other people can modify that?

I was hoping partial reconfiguration be appropriate for this. 

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Moderator
Moderator
1,354 Views
Registered: ‎11-04-2010

Re: Different partial bit streams for one partial reconfigurable partition

Jump to solution

Hi, @hanieh_jafarzadeh ,

It looks that your customer and you are working as team-design. Please consider the below points:

1. What your customer and you should decide:

   <1> All the possible ports required in all the RMs of RP.

   <2> The pblock for RP in the design.

2. You should send your new static synth dcp and top constraints to your customer if you change anything in the static part.

3. Your customer should run implement for his RM with your latest static design. 

4. Since the design will be reconfigured remotely, you have to create decouple logic to avoid data corruption during reconfiguration.

-------------------------------------------------------------------------
Don't forget to reply, kudo, and accept as solution.
-------------------------------------------------------------------------

View solution in original post

1,158 Views
Registered: ‎06-08-2018

Re: Different partial bit streams for one partial reconfigurable partition

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Hi, @hongh

Tnx for your clear reply

just another question, according to what you said, some ports can be unused. 

Should I tell my customers to consider something (like inserting a LUT in every unused port)?

 

 

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Moderator
Moderator
1,142 Views
Registered: ‎11-04-2010

Re: Different partial bit streams for one partial reconfigurable partition

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Hi, @hanieh_jafarzadeh ,

You are welcome.

A Reconfigurable Partition must contain a super set of all pins to be used by the varying Reconfigurable Modules implemented for the partition. 
If an RM uses different inputs or outputs from another RM, the resulting RM inputs or outputs might not connect inside of the RM. 
The tools handle this by inserting a LUT1 buffer within the RM for all unused inputs and outputs. The output LUT1 is tied to a constant value and the value of the constant can be controlled by HD.PARTPIN_TIEOFF property on the unused output pin.

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