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gayathri90
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Registered: ‎01-18-2014

Dynamically varying the interconnects in FPGA

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Hello everybody,

 

I have a doubt in partial reconfiguration concept and would like to get it clarified. Recently i came across an ieee paper which was discussing the reconfiguring interconnects between different modules in the design.

 

I have read about and implemented modular based PR where we define a region : the reconfigurable partition and change its functionality using reconfigurable modules on the fly.

 

But, i couldn't find any material on reconfiguring the interconnects. If somebody is familiar with the concept can you please help me in understanding this?

 

 

thanks in advance.

 

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gayathri90
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Registered: ‎01-18-2014

found the answer for my question.. :)

 

it is possible by front end difference based partial reconfiguration.

 

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vemulad
Xilinx Employee
Xilinx Employee
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Registered: ‎09-20-2012

Hi,

 

In partial reconfiguration flow the interconnects are reconfigured when you dump a different partial bitstream of the RP. However the static logic/interconnect remains the same.

 

Thanks,

Deepika.

Thanks,
Deepika.
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gayathri90
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Registered: ‎01-18-2014

Hi..

 

maybe i was not  clear enough in discussing my question.

 

Say i have 3 modules. In the first cnfiguration, i am connecting 1-2 and 1-3. In the next configuration i want to connect as 1-2-3 without any change in functionality.

 

I hope this would only change the interconnect. In that case, is there any change in the normal PR procedure?

 

Thanks

 

 

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gayathri90
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Registered: ‎01-18-2014
is there anybody to help?
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gayathri90
Explorer
Explorer
15,190 Views
Registered: ‎01-18-2014

found the answer for my question.. :)

 

it is possible by front end difference based partial reconfiguration.

 

View solution in original post

0 Kudos