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Participant leonardo_suriano
Participant
3,754 Views
Registered: ‎01-13-2017

ERROR: [DRC 23-20] Rule violation during implementation of a Partial Reconfiguration of an IP generated with HLS. problem with the module "floating_point_v7_1_0"

I am working with Vivado 2015.3 on a Win7 OS.

I created custom IPs for video processing using HLS 2015.3. After I tested every IP in a real project using a ZedBoard (and a Zybo as well) so I am sure that it is possible to complete the generation of working bitstreams with every specific IPs.

The problem is when I try to use the Xilinx Work Flow for a Partial Reconfiguration: it works as ever until, during the implementation step, it meets a vhdl module "floating_point_v7_1_0". Of course it is impossible to read it and to edit it because it is encrypted ("Xilinx Encryption Tool 2014"). The exact message is

- ERROR: [DRC 23-20] (INBB-3)  Black Box Instances - Cell '../.../../floating_point_v7_1_0' has undefined contents and it is considered as a black box. The contents of the cell must be defined for opt_design to complete succesfully.

How can I complete succesfully the generation of every partial bitstream?

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3 Replies
Participant leonardo_suriano
Participant
3,720 Views
Registered: ‎01-13-2017

Re: ERROR: [DRC 23-20] Rule violation during implementation of a Partial Reconfiguration of an IP generated with HLS. problem with the module "floating_point_v7_1_0"

update : log file "..opt_design.log"" (if needed also I can share all the source files of the design and the scripts tcl used)

 

Command: opt_design
Attempting to get a license for feature 'Implementation' and/or device 'xc7z020'
INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020'
INFO: [Common 17-1223] The version limit for your license is '2016.12' and will expire in -13 days. A version limit expiration means that, although you may be able to continue to use the current version of tools or IP with this license, you will not be eligible for any updates or new releases.
Attempting to get a license: PartialReconfiguration
INFO: [Common 17-1223] The version limit for your license is '2015.10' and will expire in -440 days. A version limit expiration means that, although you may be able to continue to use the current version of tools or IP with this license, you will not be eligible for any updates or new releases.
Feature available: PartialReconfiguration
Running DRC as a precondition to command opt_design

Starting DRC Task
INFO: [DRC 23-27] Running DRC with 2 threads
ERROR: [DRC 23-20] Rule violation (INBB-3) Black Box Instances - Cell 'design_1_i/hls_filter_0/inst/hls_filter_CalCim144_U0/hls_filter_dmul_64ns_64ns_64_6_max_dsp_U150/hls_filter_ap_dmul_4_max_dsp_64_u/U0' of type 'design_1_i/hls_filter_0/inst/hls_filter_Threshold_480_640_5_0_U0/hls_filter_fcmp_32ns_32ns_1_1_U158/hls_filter_ap_fcmp_0_no_dsp_32_u/U0/floating_point_v7_1_0' has undefined contents and is considered a black box. The contents of this cell must be defined for opt_design to complete successfully.
ERROR: [DRC 23-20] Rule violation (INBB-3) Black Box Instances - Cell 'design_1_i/hls_filter_0/inst/hls_filter_CalCim144_U0/hls_filter_dmul_64ns_64ns_64_6_max_dsp_U151/hls_filter_ap_dmul_4_max_dsp_64_u/U0' of type 'design_1_i/hls_filter_0/inst/hls_filter_Threshold_480_640_5_0_U0/hls_filter_fcmp_32ns_32ns_1_1_U158/hls_filter_ap_fcmp_0_no_dsp_32_u/U0/floating_point_v7_1_0' has undefined contents and is considered a black box. The contents of this cell must be defined for opt_design to complete successfully.
ERROR: [DRC 23-20] Rule violation (INBB-3) Black Box Instances - Cell 'design_1_i/hls_filter_0/inst/hls_filter_CalCim144_U0/hls_filter_dsub_64ns_64ns_64_5_full_dsp_U149/hls_filter_ap_dsub_3_full_dsp_64_u/U0' of type 'design_1_i/hls_filter_0/inst/hls_filter_Threshold_480_640_5_0_U0/hls_filter_fcmp_32ns_32ns_1_1_U158/hls_filter_ap_fcmp_0_no_dsp_32_u/U0/floating_point_v7_1_0' has undefined contents and is considered a black box. The contents of this cell must be defined for opt_design to complete successfully.
ERROR: [DRC 23-20] Rule violation (INBB-3) Black Box Instances - Cell 'design_1_i/hls_filter_0/inst/hls_filter_CalCim144_U0/hls_filter_fadd_32ns_32ns_32_5_full_dsp_U136/hls_filter_ap_fadd_3_full_dsp_32_u/U0' of type 'design_1_i/hls_filter_0/inst/hls_filter_Threshold_480_640_5_0_U0/hls_filter_fcmp_32ns_32ns_1_1_U158/hls_filter_ap_fcmp_0_no_dsp_32_u/U0/floating_point_v7_1_0' has undefined contents and is considered a black box. The contents of this cell must be defined for opt_design to complete successfully.
ERROR: [DRC 23-20] Rule violation (INBB-3) Black Box Instances - Cell 'design_1_i/hls_filter_0/inst/hls_filter_CalCim144_U0/hls_filter_fmul_32ns_32ns_32_4_max_dsp_U138/hls_filter_ap_fmul_2_max_dsp_32_u/U0' of type 'design_1_i/hls_filter_0/inst/hls_filter_Threshold_480_640_5_0_U0/hls_filter_fcmp_32ns_32ns_1_1_U158/hls_filter_ap_fcmp_0_no_dsp_32_u/U0/floating_point_v7_1_0' has undefined contents and is considered a black box. The contents of this cell must be defined for opt_design to complete successfully.
ERROR: [DRC 23-20] Rule violation (INBB-3) Black Box Instances - Cell 'design_1_i/hls_filter_0/inst/hls_filter_CalCim144_U0/hls_filter_fmul_32ns_32ns_32_4_max_dsp_U139/hls_filter_ap_fmul_2_max_dsp_32_u/U0' of type 'design_1_i/hls_filter_0/inst/hls_filter_Threshold_480_640_5_0_U0/hls_filter_fcmp_32ns_32ns_1_1_U158/hls_filter_ap_fcmp_0_no_dsp_32_u/U0/floating_point_v7_1_0' has undefined contents and is considered a black box. The contents of this cell must be defined for opt_design to complete successfully.
ERROR: [DRC 23-20] Rule violation (INBB-3) Black Box Instances - Cell 'design_1_i/hls_filter_0/inst/hls_filter_CalCim144_U0/hls_filter_fmul_32ns_32ns_32_4_max_dsp_U140/hls_filter_ap_fmul_2_max_dsp_32_u/U0' of type 'design_1_i/hls_filter_0/inst/hls_filter_Threshold_480_640_5_0_U0/hls_filter_fcmp_32ns_32ns_1_1_U158/hls_filter_ap_fcmp_0_no_dsp_32_u/U0/floating_point_v7_1_0' has undefined contents and is considered a black box. The contents of this cell must be defined for opt_design to complete successfully.
ERROR: [DRC 23-20] Rule violation (INBB-3) Black Box Instances - Cell 'design_1_i/hls_filter_0/inst/hls_filter_CalCim144_U0/hls_filter_fmul_32ns_32ns_32_4_max_dsp_U141/hls_filter_ap_fmul_2_max_dsp_32_u/U0' of type 'design_1_i/hls_filter_0/inst/hls_filter_Threshold_480_640_5_0_U0/hls_filter_fcmp_32ns_32ns_1_1_U158/hls_filter_ap_fcmp_0_no_dsp_32_u/U0/floating_point_v7_1_0' has undefined contents and is considered a black box. The contents of this cell must be defined for opt_design to complete successfully.
ERROR: [DRC 23-20] Rule violation (INBB-3) Black Box Instances - Cell 'design_1_i/hls_filter_0/inst/hls_filter_CalCim144_U0/hls_filter_fmul_32ns_32ns_32_4_max_dsp_U142/hls_filter_ap_fmul_2_max_dsp_32_u/U0' of type 'design_1_i/hls_filter_0/inst/hls_filter_Threshold_480_640_5_0_U0/hls_filter_fcmp_32ns_32ns_1_1_U158/hls_filter_ap_fcmp_0_no_dsp_32_u/U0/floating_point_v7_1_0' has undefined contents and is considered a black box. The contents of this cell must be defined for opt_design to complete successfully.
ERROR: [DRC 23-20] Rule violation (INBB-3) Black Box Instances - Cell 'design_1_i/hls_filter_0/inst/hls_filter_CalCim144_U0/hls_filter_fpext_32ns_64_1_U147/hls_filter_ap_fpext_0_no_dsp_32_u/U0' of type 'design_1_i/hls_filter_0/inst/hls_filter_Threshold_480_640_5_0_U0/hls_filter_fcmp_32ns_32ns_1_1_U158/hls_filter_ap_fcmp_0_no_dsp_32_u/U0/floating_point_v7_1_0' has undefined contents and is considered a black box. The contents of this cell must be defined for opt_design to complete successfully.
ERROR: [DRC 23-20] Rule violation (INBB-3) Black Box Instances - Cell 'design_1_i/hls_filter_0/inst/hls_filter_CalCim144_U0/hls_filter_fpext_32ns_64_1_U148/hls_filter_ap_fpext_0_no_dsp_32_u/U0' of type 'design_1_i/hls_filter_0/inst/hls_filter_Threshold_480_640_5_0_U0/hls_filter_fcmp_32ns_32ns_1_1_U158/hls_filter_ap_fcmp_0_no_dsp_32_u/U0/floating_point_v7_1_0' has undefined contents and is considered a black box. The contents of this cell must be defined for opt_design to complete successfully.
ERROR: [DRC 23-20] Rule violation (INBB-3) Black Box Instances - Cell 'design_1_i/hls_filter_0/inst/hls_filter_CalCim144_U0/hls_filter_fptrunc_64ns_32_1_U146/hls_filter_ap_fptrunc_0_no_dsp_64_u/U0' of type 'design_1_i/hls_filter_0/inst/hls_filter_Threshold_480_640_5_0_U0/hls_filter_fcmp_32ns_32ns_1_1_U158/hls_filter_ap_fcmp_0_no_dsp_32_u/U0/floating_point_v7_1_0' has undefined contents and is considered a black box. The contents of this cell must be defined for opt_design to complete successfully.
ERROR: [DRC 23-20] Rule violation (INBB-3) Black Box Instances - Cell 'design_1_i/hls_filter_0/inst/hls_filter_CalCim144_U0/hls_filter_fsub_32ns_32ns_32_5_full_dsp_U137/hls_filter_ap_fsub_3_full_dsp_32_u/U0' of type 'design_1_i/hls_filter_0/inst/hls_filter_Threshold_480_640_5_0_U0/hls_filter_fcmp_32ns_32ns_1_1_U158/hls_filter_ap_fcmp_0_no_dsp_32_u/U0/floating_point_v7_1_0' has undefined contents and is considered a black box. The contents of this cell must be defined for opt_design to complete successfully.
ERROR: [DRC 23-20] Rule violation (INBB-3) Black Box Instances - Cell 'design_1_i/hls_filter_0/inst/hls_filter_CalCim144_U0/hls_filter_sitofp_32ns_32_6_U143/hls_filter_ap_sitofp_4_no_dsp_32_u/U0' of type 'design_1_i/hls_filter_0/inst/hls_filter_Threshold_480_640_5_0_U0/hls_filter_fcmp_32ns_32ns_1_1_U158/hls_filter_ap_fcmp_0_no_dsp_32_u/U0/floating_point_v7_1_0' has undefined contents and is considered a black box. The contents of this cell must be defined for opt_design to complete successfully.
ERROR: [DRC 23-20] Rule violation (INBB-3) Black Box Instances - Cell 'design_1_i/hls_filter_0/inst/hls_filter_CalCim144_U0/hls_filter_sitofp_32ns_32_6_U144/hls_filter_ap_sitofp_4_no_dsp_32_u/U0' of type 'design_1_i/hls_filter_0/inst/hls_filter_Threshold_480_640_5_0_U0/hls_filter_fcmp_32ns_32ns_1_1_U158/hls_filter_ap_fcmp_0_no_dsp_32_u/U0/floating_point_v7_1_0' has undefined contents and is considered a black box. The contents of this cell must be defined for opt_design to complete successfully.
ERROR: [DRC 23-20] Rule violation (INBB-3) Black Box Instances - Cell 'design_1_i/hls_filter_0/inst/hls_filter_CalCim144_U0/hls_filter_sitofp_32ns_32_6_U145/hls_filter_ap_sitofp_4_no_dsp_32_u/U0' of type 'design_1_i/hls_filter_0/inst/hls_filter_Threshold_480_640_5_0_U0/hls_filter_fcmp_32ns_32ns_1_1_U158/hls_filter_ap_fcmp_0_no_dsp_32_u/U0/floating_point_v7_1_0' has undefined contents and is considered a black box. The contents of this cell must be defined for opt_design to complete successfully.
ERROR: [DRC 23-20] Rule violation (INBB-3) Black Box Instances - Cell 'design_1_i/hls_filter_0/inst/hls_filter_Threshold_480_640_5_0_U0/hls_filter_fcmp_32ns_32ns_1_1_U158/hls_filter_ap_fcmp_0_no_dsp_32_u/U0' of type 'design_1_i/hls_filter_0/inst/hls_filter_Threshold_480_640_5_0_U0/hls_filter_fcmp_32ns_32ns_1_1_U158/hls_filter_ap_fcmp_0_no_dsp_32_u/U0/floating_point_v7_1_0' has undefined contents and is considered a black box. The contents of this cell must be defined for opt_design to complete successfully.
INFO: [Project 1-461] DRC finished with 17 Errors
INFO: [Project 1-462] Please refer to the DRC report (report_drc) for more information.
ERROR: [Vivado_Tcl 4-78] Error(s) found during DRC. Opt_design not run.

Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.390 . Memory (MB): peak = 1220.684 ; gain = 0.000
INFO: [Common 17-83] Releasing license: Implementation
1373 Infos, 321 Warnings, 2 Critical Warnings and 18 Errors encountered.
opt_design failed

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Observer kwame.kyere
Observer
884 Views
Registered: ‎02-24-2016

Re: ERROR: [DRC 23-20] Rule violation during implementation of a Partial Reconfiguration of an IP generated with HLS. problem with the module "floating_point_v7_1_0"

Please, has this question been answered anywhere? Or perhaps were you able to solve it yourself? If this was the case, please how did you go about it?

 

Thank you.

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Xilinx Employee
Xilinx Employee
822 Views
Registered: ‎11-17-2008

Re: ERROR: [DRC 23-20] Rule violation during implementation of a Partial Reconfiguration of an IP generated with HLS. problem with the module "floating_point_v7_1_0"

This type of error will occur whenever a design is incomplete, where it is a PR design or not.  Design elements are missing here at the opt_design step and must be linked in before proceeding.  In this case, this floating point module is missing, so a netlist or library element that describes it's behavior must be inserted to complete the logical design. A netlist that represents the floating_point_v7_1_0 module must be linked in before opt_design is run, completing the full design description.  My suggestion for this original case is to review synthesis messages to find out when and why this module was missed.

 

The only time that "black box" modules are permitted in implementation (that I can think of) is when a Reconfigurable Partition (RP) is left "empty" while other RPs are implemented with new modules, but even then we require these to be defined as grey boxes.  Running update_design -buffer_ports will insert tie-off logic so the box isn't actually empty.

 

thanks,

david.