03-12-2010 12:55 AM
I am using xilinx 10.1. At thefloorplan, i am getting this error
mdc_slave : IO is using a clock buffer but is not placed in global clock type pin
mdc_slave is connected to a regular IO in bank 3 in spartan 3AN. however, in the code, i am triggering on the positive edge of this signal.
No where in the code have a buffered mdc_slave with IBUFG or any other buffer.
Why do you think this error is happening ?
03-16-2010 11:47 AM
Due to you triggering on the positive edge of this signal, your synthesis tool may have identified this signal as a clock and inserted a BUFG as a result. You may want to check your synthesis tool's netlist viewer to verify this behavior. If this is happening and it is not the desired behavior, you can turn off global buffer insertion by associating a compiler directive with that net. The specific compiler directive to be used will be dependent on the synthesis tool you're using.
04-08-2010 10:51 AM