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bkazour
Contributor
Contributor
10,179 Views
Registered: ‎01-05-2010

Floorplan Error

Hello,

I am using xilinx 10.1. At thefloorplan, i am getting this error

 

mdc_slave : IO is using a clock buffer but is not placed in global clock type pin

 

mdc_slave is connected to a regular IO in bank 3 in spartan 3AN. however, in the code, i am triggering on the positive edge of this signal.

No where in the code have a buffered mdc_slave with IBUFG or any other buffer.

Why do you think this error is happening ?

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2 Replies
hobson
Xilinx Employee
Xilinx Employee
10,151 Views
Registered: ‎04-15-2008

bkazour,

 

Due to you triggering on the positive edge of this signal, your synthesis tool may have identified this signal as a clock and inserted a BUFG as a result.  You may want to check your synthesis tool's netlist viewer to verify this behavior.  If this is happening and it is not the desired behavior, you can turn off global buffer insertion by associating a compiler directive with that net.  The specific compiler directive to be used will be dependent on the synthesis tool you're using.

 

Regards,

-Hobson

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daughtry
Xilinx Employee
Xilinx Employee
10,079 Views
Registered: ‎03-24-2008

You likely have a bufg assigned to a non-clock capable io.  As Hobson points out, make sure you intended to infer a clock in synthesis, or go into the device or package view and change the location constraint.
Greg Daughtry
Vivado Product Marketing Director, Xilinx, Inc.
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