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Explorer
Explorer
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Registered: ‎09-08-2009

HDL implementation of a generic maximum power consuming block

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I am asked to implement a design that consumes a lot of power to check the mechanical cooling design.

  • could be used for smaller or bigger FPGAs.
  • could be instantiated for instance 1000 times, 10.000 times 

 

I am thinking of designing an HDL block that could have 3 seperate entitys that could be instantiated depending on the FPGA type.

  • entity that uses single block ram, with a lot of reads and writes, each cycle interved data
  • entity that uses 2 LUTs and 4 registers with a lot of bit toggles. 
  • entity that uses one DSP without inferring it (multiply +add operations, no IP usage, a lot of toggles)

Any suggestions/comments?

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Scholar
Scholar
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Registered: ‎09-16-2009

Re: HDL implementation of a generic maximum power consuming block

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See this thread.  https://forums.xilinx.com/t5/Virtex-Family-FPGAs-Archived/Heater/td-p/740143 

Pedro's "Heater" title/keyword makes his (useful!) post a bit google unfriendly.  I'd remembered reading the post, but had a devil of a time finding it again in the forums...  Even though "heater" is kind of an effective term at what he's doing (and you're desiring.)

I've download his example, thinking I might eventually need it at one point, but have not used it as yet.

Regards,

Mark

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Registered: ‎06-21-2017

Re: HDL implementation of a generic maximum power consuming block

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How code this and what you code is only a part of the problem.  Remember, unless the FPGA has outputs that are driven by this logic, all of the logic will be optimiazed away in synthesis and you will have an empty (and cool) FPGA. 

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Explorer
Explorer
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Registered: ‎09-08-2009

Re: HDL implementation of a generic maximum power consuming block

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Thats true. I know that the logic should not be optimized away. Best way is to check what the design is synthesized into and later checking the warnings.
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Scholar
Scholar
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Registered: ‎09-16-2009

Re: HDL implementation of a generic maximum power consuming block

Jump to solution

See this thread.  https://forums.xilinx.com/t5/Virtex-Family-FPGAs-Archived/Heater/td-p/740143 

Pedro's "Heater" title/keyword makes his (useful!) post a bit google unfriendly.  I'd remembered reading the post, but had a devil of a time finding it again in the forums...  Even though "heater" is kind of an effective term at what he's doing (and you're desiring.)

I've download his example, thinking I might eventually need it at one point, but have not used it as yet.

Regards,

Mark

View solution in original post