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lucc2
Contributor
Contributor
141 Views
Registered: ‎11-29-2019

LVDS* show up in red in vivado, HighPerformance bank, Ultrascale+ MPSoC

I am having problem assigning some LVDS* signals

They always show in red in vivado looked at other post but did not find the answer on how to fix.

These are IO in High Performance bank.

 

Any pointers?

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3 Replies
bruce_karaffa
Scholar
Scholar
135 Views
Registered: ‎06-21-2017

What version of Vivado.  Are the signals inputs or outputs?  What voltage is powering the bank?  What other IO standards are used in this bank?  Are you using the internal termination resistors?

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bpatil
Xilinx Employee
Xilinx Employee
59 Views
Registered: ‎03-07-2018

Hi @lucc2 

Along with details requested by @bruce_karaffa, Error message details and snapshot will be very much helpful to understand issue. 

Regards,
Bhushan

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sandrao
Community Manager
Community Manager
43 Views
Registered: ‎08-08-2007

Hi @lucc2 

bruce_karaffa is as usual spot with his questions. The version of Vivado is very relevant. 

I filed a Change Request against 2020.1 as I had seen the same behaviour, the IOs would turn Red but when you run the DRC no issues are flagged.

The issue was resolved in 2020.2. 

I would suggest starting with running the DRC, if there is a DRC flagged then the IOs should be showing up at Red. Then bruce_karaffa's other questions is what you need to look at, direction/voltage/IOSTANDARD/Termination. 

sandrao_0-1623401401827.png

 

Thanks,

Sandy


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