04-11-2019 10:22 AM
Thank you for reading my question. I have a design that I build using the partial reconfiguration flow, targeting the ZCU102. I opened the static design DCP in Vivado 2018.2 and selected a Pblock that I defined before. Vivado reports in the "Pblock properties" view that it contains 24 RAMB36, of which 0 are used. Moreover, the entire Pblock resides in clock region X0Y3.
The Pblock is assigned the following ranges:
Now, I try to fill the Pblock with a synthesized module that uses 23 RAMB36, and I place the design with the following commands:
update_design -cell floorplan_static_i/leaf_empty_26/inst -black_box
read_checkpoint -cell floorplan_static_i/leaf_empty_26/inst bin_dense_wt_11_leaf_netlist_48.dcp
Unfortunately, placement fails. It gives the following error:
Number of BRAM required by this constraint: 23
Number of BRAM available in this constraint region: 20
Number of BRAM blocked in this constraint region: 8
Utilization = 115%
Some of the BRAMs are cascaded BRAMs in SYSTOLIC or PIPELINED mode that cannot cross clock region boundaries for timing reasons. This adds additional placement constraints.
Although the blocked BRAMs concern me, at this moment, a more pressing issue is that Vivado complains that there are only 20 BRAMs available in the Pblock whereas there should be 24. Does anybody have any idea where the other 4 might have gone?
Attached are the Vivado log, the TCL file used for placement, and a constraints file that I generated from the static design DCP. If you need more information, please let me know.
04-15-2019 12:08 AM
Hi, @hansgiesen ,
Have you tried to use bin_dense_wt_11_leaf_netlist_48.dcp as the initial configuration RM?