UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

cancel
Showing results for 
Search instead for 
Did you mean: 
Explorer
Explorer
171 Views
Registered: ‎06-08-2017

OOC module with IDELAYCTRL

I'm using the hierarchical design flow from UG905/946. I want to implement a module with ISERDESs and IDELAYs. When I try to run OOC implementation I get the following error:

HDOOC-4#1: 2 Cells are found with no placement constraints. Failure to control placement of logic with either a Pblock or a LOC constraint may result in placement conflicts if the out-of-context implementation results are reused in a top-level design. The following is a list of cells (up to the first 15) with no placement constraints:
        inputdelay (IDELAYCTRL)
        inputdelay_REPLICATED_0 (IDELAYCTRL)
inputdelay, inputdelay_REPLICATED_0

From a normal design flow I know that the IDELAYCTRLs usually go 

LOC IDELAYCTRL_X0Y0 NAME [get_cells mod0_inst/inputdelay]
LOC IDELAYCTRL_X0Y2 NAME [get_cells mod0_inst/inputdelay_REPLICATED_0]

How can I tell the placer to put the IDELAYCTRLs in these locations during OOC implementation? Or is this not necessary and I'm doing something else incorrectly?

0 Kudos