10-15-2014 03:02 AM
Hope you can you support me and sorry for long post
I have ISE14.5 and XUPV5-LX110T
A. Errors I face:
1. pr_verify step failed, I attached the pr_verify file, It includes a mismatch in the BlackBox formed in the 3rd configuration. Could you please support me in this error or where do I start debugging?
2. Kindly find another file attached for a critical warnings occurs while DRC. Are they affecting my design?
3. Attached Critical warnings for synthesing. Are they affecting my design?
B. I used to follow up with the documentation "UG743" in 12.3, 14.5 as they have some differences.
1. In 12.3 the "Count" part the Area_Group should include IOB resources because they are defined in the verilog.v files and the constraints file is divided into two, While In 14.5 the ports is assigned from top so the Area_Group not include the IOB resources? (Right - or - Wrong)
2. In 14.5 "set_param edifin.cacheNgc2Edif 0" is this needed for 14.5 and later and why? (not exist till 14.2)
3. The UCF file provided in the lab resources on xilinx training workshope (ISE14.x) some GPIO LEDs are set to 2.5v although they are 1.8v? Is this normal ?
4. I need to promote the first run (config_1) that contains the static part so the static part to be used in the other runs. The question is if I'm going to make (config_4) which use a previously implemented PR region do I need to promote (config_2) and (config_3) or implement as if they are new runs?
5. In UG743 files for virtex 6 differes from virtex 5, such that MMCM_ADV primitive exist in V6 UG362-clocking resources, Is the same Primitive supported in V5 ? because I didn't find it in the UG621 V5-HDL-Lib.
C. General Questions
1. Could I have a RM which can be used in different PR regions (same time - or - different time) ?
2. What is the difference between the GPIO leds and the leds beside the bush button?
Thanks for your time and consideration.
10-20-2014 01:35 AM
Regarding A.1. I find my problem with the pr_Verify faliar that I put (IOBUffer = No) while synthies the top view. So as a conclusion I had to set (IOBuffer = yes) while synthies top and (IOBuffer = NO) synthies RM module
Hope to find answers for the rest of questions. Espicially in B.3 , C.1 and C.2