[Place 30-859] Some BRAM area constraints are over utilized. Placer error in a partially reconfigurable design.

[s.beigmohammadi]

Hi,

I'm using Vivado 2019.2 in project mode to implement a PR design targeting ZCU106 board. A variant of the following error pops up when trying to run the placer in one of the child runs complaining about over-utilization of either DSP or BRAM resources in a reconfigurable partition. The reconfigurable partition does have enough DSP/BRAM resources to accommodate the reconfigurable module.

[Place 30-859] Some BRAM area constraints are over utilized.

2 or more BRAM failed to place.
Some BRAM sites are excluded by the following pblocks. Check whether sufficient sites exist for BRAM instances not included in the exclude pblocks.
Exclude pblock 'pblock_L0': with ranges:
URAM288_X0Y32:URAM288_X0Y63
RAMB36_X1Y24:RAMB36_X1Y47
RAMB18_X1Y48:RAMB18_X1Y95
HARD_SYNC_X2Y4:HARD_SYNC_X3Y7
DSP48E2_X4Y48:DSP48E2_X6Y95
SLICE_X52Y120:SLICE_X63Y239
Exclude pblock 'pblock_M0': with ranges:
RAMB36_X2Y64:RAMB36_X3Y70
RAMB18_X2Y128:RAMB18_X3Y141
HARD_SYNC_X4Y10:HARD_SYNC_X7Y11
DSP48E2_X7Y128:DSP48E2_X12Y141
SLICE_X69Y320:SLICE_X98Y354
Exclude pblock 'pblock_M1': with ranges:
RAMB36_X2Y52:RAMB36_X3Y58
RAMB18_X2Y104:RAMB18_X3Y117
HARD_SYNC_X4Y8:HARD_SYNC_X7Y9
DSP48E2_X7Y104:DSP48E2_X12Y117
SLICE_X69Y260:SLICE_X98Y294
Exclude pblock 'pblock_S0': with ranges:
RAMB36_X0Y66:RAMB36_X0Y71
RAMB18_X0Y132:RAMB18_X0Y143
HARD_SYNC_X0Y10:HARD_SYNC_X1Y11
DSP48E2_X0Y132:DSP48E2_X0Y143
SLICE_X1Y330:SLICE_X16Y359
The unplaced BRAM are constrained as below: (listing maximum of 20 BRAMs per constraint)
Pblock 'pblock_M1':
Pblock ranges:
RAMB36_X2Y52:RAMB36_X3Y58
RAMB18_X2Y104:RAMB18_X3Y117
HARD_SYNC_X4Y8:HARD_SYNC_X7Y9
DSP48E2_X7Y104:DSP48E2_X12Y117
SLICE_X69Y260:SLICE_X98Y294
Area constraint: PBlock
M1_inst/v_proc_ss_0/inst/vsc/inst/v_vscaler_CTRL_s_axi_U/int_HwReg_vfltCoeff/gen_write[1].mem_reg
M1_inst/v_proc_ss_0/inst/hsc/inst/v_hscaler_CTRL_s_axi_U/int_HwReg_hfltCoeff/gen_write[1].mem_reg
Tile rectangles examined:
Rect: ((277, 68), (352, 103))

Number of BRAM required by this constraint: 14
Number of BRAM available in this constraint region: 10
Number of BRAM blocked in this constraint region: 16
Utilization = 140%

Some of the BRAMs are cascaded BRAMs in SYSTOLIC or PIPELINED mode that cannot cross clock region boundaries for timing reasons. This adds additional placement constraints.

[Place 30-365] The following macros could not be placed:
M1_inst/v_proc_ss_0/inst/vsc/inst/v_vscaler_CTRL_s_axi_U/int_HwReg_vfltCoeff/gen_write[1].mem_reg (RAMB36E2)
The instance has been constrained to an area with the following utilization (BRAM/DSP/URAM): 100/685.7/0
and M1_inst/v_proc_ss_0/inst/hsc/inst/v_hscaler_CTRL_s_axi_U/int_HwReg_hfltCoeff/gen_write[1].mem_reg (RAMB36E2)
The instance has been constrained to an area with the following utilization (BRAM/DSP/URAM): 100/685.7/0
The total BRAM utilization is 63.94, the total DSP utilization is 74.07 and the total URAM utilization is 0
A possible reason is high utilization of BRAMs, DSPs, URAMs, or RPMs. Please check user constraints to make sure design is not over-utilized in the constraint areas (if any) keeping in mind some macros require a number of consecutively available sites
ERROR: DSP utilization in constrained region pblock_M1 is greater than it's capacity. Detected utilization = 685.714 percent.

[Place 30-99] Placer failed with error: 'The following macros could not be placed:
<MSGMETA::BEGIN::BLOCK>M1_inst/v_proc_ss_0/inst/hsc/inst/v_hscaler_CTRL_s_axi_U/int_HwReg_hfltCoeff/gen_write[1].mem_reg<MSGMETA::END> (RAMB36E2)
The instance has been constrained to an area with the following utilization (BRAM/DSP/URAM): 100/685.7/0
<MSGMETA::BEGIN::BLOCK>M1_inst/v_proc_ss_0/inst/vsc/inst/v_vscaler_CTRL_s_axi_U/int_HwReg_vfltCoeff/gen_write[1].mem_reg<MSGMETA::END> (RAMB36E2)
The instance has been constrained to an area with the following utilization (BRAM/DSP/URAM): 100/685.7/0
The total BRAM utilization is 63.94, the total DSP utilization is 74.07 and the total URAM utilization is 0
A possible reason is high utilization of BRAMs, DSPs, URAMs, or RPMs. Please check user constraints to make sure design is not over-utilized in the constraint areas (if any) keeping in mind some macros require a number of consecutively available sites
ERROR: DSP utilization in constrained region pblock_M1 is greater than it's capacity. Detected utilization = 685.714 percent.
'
Please review all ERROR, CRITICAL WARNING, and WARNING messages during placement to understand the cause for failure.

I tried running opt_design -propconst -sweep -bufg_opt -shift_register_opt on the main and child runs as suggested here and it does not resolved the issue. AR#64734 (i.e., set_param place.closeImportedSites false)  does not fix the problem either. Furthermore, due to version and device differences, I cannot use the tactical patch provided for Vivado 2020.1 in AR#75389.

I have uploaded the optimized netlist DCP for the failing child run here.

I have no clue what is causing the problem. Any ideas how to resolve this issue? Can I somehow skip this placement check in the hope that the reconfigurable modules would be placed correctly?

Thanks,

Siamack

[marcb]

Hi @s.beigmohammadi 

A little background on the behavior that looks to be affecting this error. After the first configuration, BRAM and DSP sites can be blocked for usage in the second configuration. This happens if the routing resources are needed near the horizontal boarder of the RP pblock. To check where these are, the ./hd_visual/blockedbelsoutput.tcl can be used to select and highlight the blocked sites. Here are some suggestions on how to overcome the error.

1. Always make sure to have the first configuration use the most challenging Reconfigurable Module (RM). Specifically, use an RM in the initial configuration which has the highest utilization for Block RAMs and DSPs.
2. Adjust the pblock size to account for blocked sites. This could mean shifting the pblock so that the failing sites are not near the edge of the pblock where more boundary resources are needed.
3. Reduce BRAM/DSP utilization through various Vivado options/constraints.