We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

Showing results for 
Search instead for 
Did you mean: 
Observer dimple.sharma
Registered: ‎11-03-2017

Placer fails during partial reconfiguration



I am working on a partial reconfiguration based design. I first created a project without PR enabled. I assigned pblocks to the modules which I would later mark as reconfigurable. The design compiles successfully up to the generate bitstream stage.

However, when I enable PR and convert the project to a PR project, the placer fails during implementation and gives the following error:


  • [Place 30-487] The packing of instances into the device could not be obeyed. There are a total of 4200 slices in the pblock, of which 1626 slices are available, however, the unplaced instances require 1789 slices. Please analyze your design to determine if the number of LUTs, FFs, and/or control sets can be reduced. Number of control sets and instances constrained to the design Control sets: 91 Luts: 15131 (combined) 18559 (total), available capacity: 16800 Flip flops: 2429, available capacity: 33600 NOTE: each slice can only accommodate 1 unique control set so FFs cannot be packed to fully fill every slice

What could be the reason that the normal project compiles well, but the PR project fails?




0 Kudos
2 Replies
Xilinx Employee
Xilinx Employee
Registered: ‎11-17-2008

Re: Placer fails during partial reconfiguration



Two questions to start:  What is the target device architecture, and are the pblocks frame aligned?  Depending on how the pblocks are drawn, you could be allowing the tools fewer resources for the PR flow as compared to the flat flow.  For example, if you are using UltraScale, take a look at the shading within the pblock in the floorplan view when HD.RECONFIGURABLE is enabled.  Pblocks in that architecture will "snap in" to valid boundaries, and anything not shaded is returned to the static design.  So perhaps the flat version of the design has more than the 4200 slices that are available in the PR version.


Another question: how is synthesis and optimization done?  PR requires a firm explicit boundary between static and reconfigurable to ensure that we can swap in a new module with the same virtual interface.  So with this flow we cannot perform logic optimizations across the boundary like we can with a flat flow.  Take a look at the resources in your design after optimization and make sure you're comparing apples to apples.  Perhaps there are fewer than 1626 slices required for the flat version after optimization.




Observer dimple.sharma
Registered: ‎11-03-2017

Re: Placer fails during partial reconfiguration

Hi David,


Thanks for the reply. 


I am working on the Zedboard (Zynq 7020) and using Vivado 17.4. 

The design without PR fit well in the gray regions of the pblocks. However, with the exact same design; the placer failed. 


The boundary between static and the partially reconfigurable regions seems to be well defined; I used the PR project flow the Vivado 17.4 version. The entire process was smooth until the implementation stage.


I had 4 reconfigurable regions, and there was a clock enable to every region. When I took away all the clock enables from the design (VHDL code), the implementation was successful and the bit-streams were generated.


Another observation; I also have a clocking wizard in my design, with dynamic reconfiguration of the clock selected. 

The placer again failed when I selected the 'Phase Duty Cycle config' in the 'clocking options' tab of the wizard.

But when I unchecked that option; the implementation was again successful.


I am unable to understand why the clock enables or the phase/duty cycle config selection would affect the placer.


Thank you,




0 Kudos