01-19-2010 12:48 PM
I start with a pre-defined net .ucf file, from ISE, I open it in PlanAhead and identify which of my signals are to be differential. After passing RunDRC, I quit the tool.
How do I pass back these IO changes to the ISE. If I re-invoke the tool, all my changes have been lost.
01-26-2010 08:31 AM
Any thoughts on why PlanAhead-pre-synthesis changes to the IO are not being saved back to ISE?
Appreciate any insight. Thanks!!
02-01-2010 05:10 AM
I haven't used PlanAhead from ISE, but PlanAhead has an option under the file menu called "Export Constraints". You could try using that. If PlanAhead got all of your constraints from the .ucf that ISE is using, then you could just switch out the .ucf files. Otherwise you'll need to copy the modified/new constraints over.
02-09-2010 02:23 AM
I had such a problem too. I have two vectors for LVDS, one contains positive signals and second negative ones. During PCB development I had to change polarity (mix N and P) so I had tried to fix it by conecting in diffrent way signals from vectors in PlanAhead, and rodeo started. Configuration form pre-synthesis IO plan did not save configuration anymore. I have fixed it by not mixing vectors, so positive for positive, negative for negative. I prepare data before I send it by negating bits. Conclusion: from my point of view PlanAhead does not like to have negative and positive differential output signals in one vector.
PS. ver. ISE 11.1
04-08-2010 11:09 AM
Only UCF changes are passed back to Project Navigator in pin planning mode. If you come into planAhead with single-ended netlist, and create new ports (like turning a single ended io into differential) this is actually a netlist (edif) change. EDIF is not written back to Project Navigator projects.
You actually need to modify your RTL to get separate port signals, or.... use PlanAhead standalone and export a verilog/vhdl header file to go along with the ucf file for pin assignement. You can then use this template to modify your RTL, if you have any.