01-18-2011 02:21 PM
Hello, I'm trying to implement a Partial Reconfiguration Design. I followed the example of UG744 using the the ML605 board. Then I moved to a design using my boards (an ML501 and ML505). When I use exactly the same system configuration (MicroBlaze + SystemACE + Serial ), even with my own "reconfigurable modules", I have no problems to implement the design in PlanAhead and obtain the partial bit files.
However, when trying to add the DDR2 memory to the design, I got the following error when running the implementation for the first RP module
MapLib: 1120 - IDELAYCTRL DDR2_SDRAM/DDR2_SDRAM/gen_no_iodelay_grp.gen_instantiate_idelayctrls.idelayctrl0, DDR2_SDRAM/DDR2_SDRAM/gen_no_iodelay_grp.gen_instantiate_idelayctrls.idelayctrl0,
have no IODELAY_GROUP association. Only one IODELAY Controller may
have no LOC constraint and no IODELAY_GROUP.
Any help will be highly appreciated
01-18-2011 06:35 PM
This error is typically caused by violations of the rules for IDELAYCTRL replication.
Apparently there're more than 1 IDELAYCTRL are instantiated in your design, so please LOC each down.
01-19-2011 02:28 AM
thank you for your reply. Where am I supposed to LOC them down? In the UCF file? The funny thing is, If I implement the system without the reconfigurable partition, in EDK, it works fine. It is just when I import the design to PlanAhead that is having this problem
01-19-2011 12:41 PM
01-26-2011 07:42 AM
Hello, I solved the problem through this reponse
"I suspect there are some UCFs of the IP cores in your design in the XPS project. But you only add the top level UCF to the PlanAhead project. Try to find the IP UCFs and copy the contents to the top level UCF."
Indeed, the information of the "ddr2_sdram_wrapper" UCF was not being imported. I imported this file together with the "system.ucf" file when creating the PlanAhead project, and voilà, it has passed through MAP and PAR