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Visitor
Visitor
12,198 Views
Registered: ‎01-18-2011

PlanAhead 12.4 - Problem with MAP when doing Partial Reconfiguration

Hello, I'm trying to implement a Partial Reconfiguration Design. I followed the example of UG744 using the the ML605 board. Then I moved to a design using my boards (an ML501 and ML505). When I use exactly the same system configuration (MicroBlaze + SystemACE + Serial ), even with my own "reconfigurable modules",  I have no problems to implement the design in PlanAhead and obtain the partial bit files.

 

However, when trying to add the DDR2 memory to the design, I got the following error when running the implementation for the  first RP  module

 

 

MapLib: 1120 - IDELAYCTRL DDR2_SDRAM/DDR2_SDRAM/gen_no_iodelay_grp.gen_instantiate_idelayctrls[0].idelayctrl0, DDR2_SDRAM/DDR2_SDRAM/gen_no_iodelay_grp.gen_instantiate_idelayctrls[1].idelayctrl0,
DDR2_SDRAM/DDR2_SDRAM/gen_no_iodelay_grp.gen_instantiate_idelayctrls[2].idelayctrl0
have no IODELAY_GROUP association. Only one IODELAY Controller may
have no LOC constraint and no IODELAY_GROUP.

 

Any help will be highly appreciated

 

Gilberto Ochoa

 

 

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Xilinx Employee
Xilinx Employee
12,184 Views
Registered: ‎07-16-2008

This error is typically caused by violations of the rules for IDELAYCTRL replication.

Apparently there're more than 1 IDELAYCTRL are instantiated in your design, so please LOC each down.

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Visitor
Visitor
12,171 Views
Registered: ‎01-18-2011

 

Hello,

 

thank you for your reply. Where am I supposed to LOC them down? In the UCF file? The funny thing is, If I implement the system without the reconfigurable partition, in EDK, it works fine. It is just when I import the design to PlanAhead that is having this problem

 

Gilberto

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Xilinx Employee
Xilinx Employee
12,148 Views
Registered: ‎04-06-2010

Yes, you need to LOC them in your UCF.  If you want to know which location to LOC them to, refer to the following Xilinx Answer Record:

http://www.xilinx.com/support/answers/24704.htm

 

Hope this helps.

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Visitor
Visitor
12,078 Views
Registered: ‎01-18-2011

 

Hello, I solved the problem through this reponse

 

http://forums.xilinx.com/t5/PlanAhead/Implementation-problems-with-planAhead/m-p/69031

 

"I suspect there are some UCFs of the IP cores in your design in the XPS project. But you only add the top level UCF to the PlanAhead project. Try to find the IP UCFs and copy the contents to the top level UCF."

 

Indeed, the information of the "ddr2_sdram_wrapper" UCF was not being imported. I imported this file together with the "system.ucf" file when creating the PlanAhead project, and voilà, it has passed through MAP and PAR