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Participant
Participant
1,221 Views
Registered: ‎08-03-2017

Problem in tutorial of partial reconfigration project flow

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Hi, 

 

I have tried partial reconfiguration (PR) tutorial using UG947 (2017.4).

 

(1)

I have created project and added sources (.v and .xdc).

But, I can't make the hierarchy correct.

PR target modules (inst_shift, inst_count) are loaded from top.v.

These modules is black box in top.v and I can't create partition definition to them.

Would you tell me how to loaded from shift_right.v and count_up.v ?

 

(2)

fig.21 in UG947 (2017.4) shows PR target modules are shift_low and shift_high.

Is it old version?

 

Best Regards,

Tetsuo

pr_problem_000.jpg

 

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Participant
Participant
1,150 Views
Registered: ‎08-03-2017

I'm wrong.

There are separated sources for project flow and sources for tcl flow.

PR target module is comment on top.v for project flow.

I'm sorry, @hongh @lowearthorbit

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Highlighted
1,191 Views
Registered: ‎09-17-2018

Were you using Vivado release 2017.4?

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Moderator
Moderator
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Registered: ‎11-04-2010

Hi, @tetsuo_yamashita ,

Which top.v file are you using? 

Could you show us where top.v is stored and the content of top.v?

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Moderator
Moderator
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Registered: ‎11-04-2010

Hi, @tetsuo_yamashita ,

Do you keep the below content in the end of top.v in comments? 

 

// black box definition for module_shift
//module shift(
// input en,
// input clk,
// input [11:0] addr,
// output [3:0] data_out);
//endmodule

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Participant
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Registered: ‎08-03-2017

Thank you for your replies!

 

@lowearthorbit

I'm using Vivado 2017.4.

Vivado v2017.4 (64-bit)
SW Build: 2086221 on Fri Dec 15 20:54:30 MST 2017
IP Build: 2085800 on Fri Dec 15 22:25:07 MST 2017

 

@hongh

The path of top.v is ./ug947-vivado-partial-reconfiguration-tutorial/led_shift_count_us/Sources/hdl/top/top.v .

I'm using the top.v without editing.

Because, a procedure of editing top.v is not on the tutorial document. 

 

 

module top(
   input        clk_p,       // 200MHz differential input clock
   input        clk_n,       // 200MHz differential input clock
   input        rst_n,       // Reset mapped to center push button
   output [3:0] count_out,   // mapped to general purpose LEDs[4-7]
   output [3:0] shift_out    // mapped to general purpose LEDs[0-3]
);

......

endmodule


// black box definition for module_shift
module shift(
   input         en,
   input         clk,
   input  [11:0] addr,
   output  [3:0] data_out);
endmodule

// black box definition for module_count
module count(
   input        rst,
   input        clk,
   output [3:0] count_out);
endmodule

 

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Participant
Participant
1,151 Views
Registered: ‎08-03-2017

I'm wrong.

There are separated sources for project flow and sources for tcl flow.

PR target module is comment on top.v for project flow.

I'm sorry, @hongh @lowearthorbit

View solution in original post

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