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Visitor venka_peri
Visitor
109 Views
Registered: ‎03-27-2017

RLOC RANGE in Vivado

Hi - 

Is there a way to specify a range when constaining design elements in RTL?

I have a set of registers that I would like to constrain in my module. My (pseudo) code looks like:

module module_name

(

input.....

output.....

);

(* HU_SET = "uset0", RLOC = "X1Y0:X1Y1" , KEEP = "TRUE" *)  logic [15:0] ff1;

(* HU_SET = "uset0", RLOC = "X2Y0:X2Y1" , KEEP = "TRUE" *) logic [15:0] ff2;

 

always @ (posedge clk) begin

 ff1 <= exp1;

 ff2 <= exp2;

end

 

....

...

endmodule

 

I would like to place  ff1 and ff2 (16 flip-flops each) in contiguous slices one above the other - with 8 registers per slice

for a total of 4 slices. The above code does not work.

I get the desired result if I re-arrange/split my implementation to:

(* HU_SET = "uset0", RLOC = "X1Y0" , KEEP = "TRUE" *)  logic [15:8] ff1_msb;

(* HU_SET = "uset0", RLOC = "X1Y1" , KEEP = "TRUE" *)  logic [7:0] ff1_lsb;

(* HU_SET = "uset0", RLOC = "X2Y0" , KEEP = "TRUE" *) logic [15:8] ff2_msb;

(* HU_SET = "uset0", RLOC = "X2Y1" , KEEP = "TRUE" *) logic [7:0] ff2_lsb;

 

 I was curious to know if there is a way to pass an RLOC RANGE (in RTL in Vivado).

Thanks,

-Venka

 

 

 

 

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