05-30-2018 02:20 PM
Here's something brand new to delight the Vivado Power User.. RapidWright.
FPGA application size is rapidly growing by reuse and replication. Achieved quality of results (QoR) of these large designs is often much lower than what could be realized with localized circuits at a modular level. One underlying reason for QoR loss is that back-end implementation tools compile the designs as one large circuit entry. Is there a way to bring innovation to the implementation stage of FPGA compilation that can improve QoR?
This work proposes a pre-implemented methodology for FPGAs to achieve higher performance or productivity and introduces RapidWright, an opensource platform to enable this new approach. We aim to enhance either QoR or productivity through the reuse of modular implementations and present examples that improve QoR up to 50% or accelerate compilation time and debug by more than an order of magnitude. Finally, we demonstrate how RapidWright enables custom crafted implementations with near spec performance.
Documentation is here: http://www.rapidwright.io/docs/index.html
Flow looks something like this: The secret sauce? JAVA
05-31-2018 08:36 AM
Just a quick follow up on what @jmcclusk has stated, RapidWright is a new open source platform, developed by Xilinx Research Labs, that enables netlist and implementation manipulation of modern Xilinx FPGA and SoC designs by providing a gateway to Vivado’s back-end implementation tools. Further details can be found on the RapidWright website.
Any RapidWright inquires or support requests should be directed to the RapidWright Forum.
08-07-2018 11:10 PM
11-03-2019 12:13 PM
RapidWright is a very exciting development and I have been thinking about how to add a tool in the red "secret sauce" area. What I am considering is not so secret but a new placer which uses ML for placement as described here: https://github.com/limbo018/DREAMPlace. Would it be possible to do FPGA placement with DREAMPlace and use the Xilinx placer as refinement tool? The speed of DREAMPlace for ASIC flows seems incredible and it would really help with FPGAs too.
Any comments, suggestions would be welcome.
11-05-2019 10:21 AM