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Registered: ‎10-15-2018

Readback capture of BRAM contents fails when using Partial Reconfiguration

 

Short description:

I am trying to perform a readback capture on an AlveoU280 card through the ICAP port in order to extract the current state of BRAM and CLB register primitives. The readback of BRAM contents fails when using a design with Partial Reconfiguration, while the actual contents of BRAM primitives are correctly retrieved whenever a design with no Partial Reconfiguration is used. On the other hand, CLB registers are always correctly retrieved through a readback capture, no matter if PR is used or not.

 

Long description:

I am working on a project on an AlveoU280 board. I need to perform a readback capture to get the state of registers and BRAMs in a design with partial reconfiguration. I have developed an ICAP controller which supports both partial reconfiguration and readback. If I perform a simple readback (without capture), I can get correct data: I have verified it using the .rbd and the .msd files, and there is a perfect correspondence. However, I am having some problems with readback capture. In order to perform this operation, I am using a bitstream with the commands described in XAPP1230. Then, I use the information contained in the logic location file to identify dynamic bits inside readback data. The situation is the following:

  • I can always get the correct state for CLB registers;
  • I cannot get the correct state for BRAMs. In particular, looking at the content of every BRAM in my design, it seems to be always the same repetitive pattern. So, it looks like the content of BRAMs is somehow masked.

I have done several tests to understand why this problem occurs and I have found that:

  • This problem applies to all the BRAMs in my design, both in the static and in the dynamic region.
  • The problem is not related to the clocking of the BRAMs (I have the same problem even if I disable the clock);
  • I have tried to instantiate a BRAM primitive (with the dont_touch attribute) with a non-zero initial content. This BRAM is only connected to a clock signal, while all the other input signals are put to their inactive state. If I perform a readback capture and look at the bits corresponding to its content, I still get the usual pattern. Note that if I look at the full bitstream, I can confirm that the content of the BRAM is initialised to a non-zero value.
  • I have tried to use a pblock without any BRAM primitive for my reconfigurable partition, but the problem is still there for the BRAMs outside the pblock.
  • Then, I have repeated most of the previous tests in an identical design, but without enabling partial reconfiguration. I can always get the expected state of the BRAM.


In conclusion, the problem seems to be somehow related to partial reconfiguration. Therefore, I have explored all the different tcl files generated by Vivado for both the designs (with and without Partial Reconfiguration), to check if there are some differences in the commands used to generate both projects. However, I could not find any relevant difference that could be somehow related to the readback process.
I have performed my tests on different designs, some using an XDMA to communicate with the ICAP controller, and some others using a jtag_to_axi instead. However, the results are always the same: masked BRAM contents if using Partial Reconfiguration, actual contents if no PR is used.
I hope you could help me to find out why this problem is occurring and how I can avoid the BRAM content to be masked.
Regards.

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