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Participant
Participant
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Registered: ‎09-10-2012

Redefine parameter value at Design Run start.

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In the top-level of my project I have parameter, which affect resulting functions of device. At this time I copy top-level file several times, modify every file with it's own parameter value and create several Synth-Impl runs, one for each copy of top-level. If I need to regenerate one of project versions, I am applying "Set as Top" for needed file, then applying "Make Active" for the needed run pair and in the end starting Design Run.
Overall it's a bit messy project flow. So is there more elegant way to achieve my goal? I want to keep only one copy of top-level and define parameter value based on selected Design Run. TCL pre-run script? XDC constraint?

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Guide
Guide
7,675 Views
Registered: ‎01-23-2009

Re: Redefine parameter value at Design Run start.

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This is not a perfect solution, but its pretty good...

 

You can create multiple synthesis runs using the GUI. Each synthesis run will use the same source set and constraint set. You can then set the synthesis properties differently for each of the runs. The synth_design command (which is what is actually invoked by launching the synthesis run) has an option -generic, where you can set (really override) the value of top level parameters/generics (Verilog/VHDL). You can set this option either using the GUI (synthesis settings) or by the Tcl command

 

set_property -name {STEPS.SYNTH_DESIGN.ARGS.MORE OPTIONS} -value {-generic test=1} -objects [get_runs synth_1]

 

You can set this to a different value for each of the two runs.

 

set_property -name {STEPS.SYNTH_DESIGN.ARGS.MORE OPTIONS} -value {-generic test=2} -objects [get_runs synth_2]

 

This property is tracked by the runs manager. So once you set it on one of the runs, it will be set forever - you can re-launch synthesis (of either synthesis run) and they will retain the settings - synth_1 will always have test=1 and synth_2 will always have test=2. This way you don't need to muck around with multiple copies of the source file or Tcl scripts.

 

The reason this is not "perfect" is that the normal way to set generics is through the language options property

 

set_property generic test=1 [current_fileset]

 

But this is set on the source set, which is shared by the two runs, so you can't easily switch back and forth. The advantage of setting it in the language options is that it applies not only to synthesis, but also to simulation. Applied to the synth runs it applies only to synthesis.

 

Avrum

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Highlighted
Guide
Guide
7,676 Views
Registered: ‎01-23-2009

Re: Redefine parameter value at Design Run start.

Jump to solution

This is not a perfect solution, but its pretty good...

 

You can create multiple synthesis runs using the GUI. Each synthesis run will use the same source set and constraint set. You can then set the synthesis properties differently for each of the runs. The synth_design command (which is what is actually invoked by launching the synthesis run) has an option -generic, where you can set (really override) the value of top level parameters/generics (Verilog/VHDL). You can set this option either using the GUI (synthesis settings) or by the Tcl command

 

set_property -name {STEPS.SYNTH_DESIGN.ARGS.MORE OPTIONS} -value {-generic test=1} -objects [get_runs synth_1]

 

You can set this to a different value for each of the two runs.

 

set_property -name {STEPS.SYNTH_DESIGN.ARGS.MORE OPTIONS} -value {-generic test=2} -objects [get_runs synth_2]

 

This property is tracked by the runs manager. So once you set it on one of the runs, it will be set forever - you can re-launch synthesis (of either synthesis run) and they will retain the settings - synth_1 will always have test=1 and synth_2 will always have test=2. This way you don't need to muck around with multiple copies of the source file or Tcl scripts.

 

The reason this is not "perfect" is that the normal way to set generics is through the language options property

 

set_property generic test=1 [current_fileset]

 

But this is set on the source set, which is shared by the two runs, so you can't easily switch back and forth. The advantage of setting it in the language options is that it applies not only to synthesis, but also to simulation. Applied to the synth runs it applies only to synthesis.

 

Avrum

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Participant
Participant
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Registered: ‎09-10-2012

Re: Redefine parameter value at Design Run start.

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That's exactly what I need. Thank you very much.
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