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Registered: ‎01-10-2017

Reusing partial reconfiguration modules in a single design

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Hi

 

I have a design that will need several reconfigurable functions, but then also 32 sites on the chip that need to be reconfigured with one of these functions.

 

Is it possible to define “similar” sites that can all use the same set of PR functions, or must a set of these functions be generated for each of the 32 sites individually?

 

Many thanks,

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Xilinx Employee
Xilinx Employee
7,533 Views
Registered: ‎04-16-2008

Re: Reusing partial reconfiguration modules in a single design

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Hi Kevin,

 

What you are describing we refer to as "relocatable partial bitstreams".  For several reasons (including the fact that the Static region is allowed to use routing resources inside of the reconfigurable regions) this is complex use case, and one that we do not currently support.

 

You can synthesize each of the RMs once, but each RM will need to be implemented in each site once.  However, you don't need to implement every scenario. In your case, if you have 3 RMs, you will need three configurations (implementations).  

  1. Configuration 1 - Implement Static along with RM1 in all 32 RPs
  2. Configuration 2 - Import Static from Config 1, use RM2 for all 32 RPs
  3. Configuration 3 - Import Static from Config 1, use RM3 for all 32 RPs

This will allow you to create any combination you want in hardware (eg. RP1 --> RM1, RP2--> RM3, RP3-->RM2).  The more RMs you have, the more runs you will need to have. It also means you will need to manage 32x3 partial bit files, and keep track of which bit files belong to which RP.  

 

Xilinx is aware of how relocatable bitstreams could simply a scenario like this (especially relative to bitstream management), but there are also tradeoffs in QoR for this type of solution as well.

 

If you have any additional details you could share about your design requirements, and desire for relocatable bitstreams, we can capture those requirements for future consideration.

 

Hope this helps.

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Xilinx Employee
Xilinx Employee
7,534 Views
Registered: ‎04-16-2008

Re: Reusing partial reconfiguration modules in a single design

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Hi Kevin,

 

What you are describing we refer to as "relocatable partial bitstreams".  For several reasons (including the fact that the Static region is allowed to use routing resources inside of the reconfigurable regions) this is complex use case, and one that we do not currently support.

 

You can synthesize each of the RMs once, but each RM will need to be implemented in each site once.  However, you don't need to implement every scenario. In your case, if you have 3 RMs, you will need three configurations (implementations).  

  1. Configuration 1 - Implement Static along with RM1 in all 32 RPs
  2. Configuration 2 - Import Static from Config 1, use RM2 for all 32 RPs
  3. Configuration 3 - Import Static from Config 1, use RM3 for all 32 RPs

This will allow you to create any combination you want in hardware (eg. RP1 --> RM1, RP2--> RM3, RP3-->RM2).  The more RMs you have, the more runs you will need to have. It also means you will need to manage 32x3 partial bit files, and keep track of which bit files belong to which RP.  

 

Xilinx is aware of how relocatable bitstreams could simply a scenario like this (especially relative to bitstream management), but there are also tradeoffs in QoR for this type of solution as well.

 

If you have any additional details you could share about your design requirements, and desire for relocatable bitstreams, we can capture those requirements for future consideration.

 

Hope this helps.

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4,007 Views
Registered: ‎01-10-2017

Re: Reusing partial reconfiguration modules in a single design

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Yes, thanks!

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