05-20-2019 01:11 PM
I have Vivado project with block design and a number of IPs. One of them was created from a single RTL file. The block design has been validated and generated. When I tried to synthesize the project, I got the error messages that Vivado cannot find .v and .dcp files for this IP. All IPs were packaged and generated the same way. Why .dcp has not been originally generated and how to enforce its generation?
Why the tool is complaining about .v file if I see it in the target directory: ...\COSMO_GOLDEN.srcs\sources_1\bd\COSMO_FPGA\ip\COSMO_FPGA_GPMC_IF_0_0\synth\ COSMO_FPGA_GPMC_IF_0_0.v?
05-20-2019 10:47 PM - edited 05-20-2019 10:56 PM
From the messages window,
the error [SYNTH 8 - 439] says that while synthesizing the module COSMO_FPGA_GPMA_IF_0_0
a submodule by the name GPMC_IF is not found, can you correct this and then try again.
you said that IP was packaged using a single RTL file, then why is synthesis trying to look for GPMC_IF (module) RTL file ?
It would be helpful if you share with us the hierarchy and Log file
05-21-2019 04:00 PM
I do not know what Vivado is doing. Now the tool does not complain about the missing .dcp file (which is still missing although I re-generated IP with OOC and generated Output Products for BD).
I have attached the log files. Should I expect the missing files if the BD was validated and generated?
The GPMC_IF is not an RTL file, it is a name of IP.