03-16-2017 10:39 AM
I'm new to system generator. Now I want to save sampled 32 bits data generated from system generator into FIFO which is already existing in Vivado project.
In order to write data into FIFO, I need not only 32 bits data from system generator but also write enable signal and the sample clock from system generator. It seems that only 32 bits data can be outputted from system generator.
What should I do?
03-16-2017 11:28 AM
03-17-2017 01:17 AM
Hi, thank you for your reply. What is more important is the clock signal, which should also come from SYSTEM GENERATOR. But I cannot get it from SYSTEM GENERATOR. If data coming from SYSTEM GENERATOR is changed at rising edge of external wr_clk, then it maybe have risk of errors, I think.