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Visitor liuyanbc157
Visitor
3,022 Views
Registered: ‎02-01-2017

System generator: output data to FIFO in vavado

Hi, everybody,

 

I'm new to system generator. Now I want to save sampled 32 bits data generated from system generator into FIFO which is already existing in Vivado project.

 

In order to write data into FIFO, I need not only 32 bits data from system generator but also write enable signal and the sample clock from system generator.  It seems that only 32 bits data can be outputted from system generator.

 

What should I do?

 

Thanks alot.

 

YL

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2 Replies
Xilinx Employee
Xilinx Employee
3,012 Views
Registered: ‎08-01-2008

Re: System generator: output data to FIFO in vavado

there is no such limitation . in case you want to use AXI which only supports 32 bits . you can generate enable signal in sysgen
Thanks and Regards
Balkrishan
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Visitor liuyanbc157
Visitor
2,989 Views
Registered: ‎02-01-2017

Re: System generator: output data to FIFO in vavado

@balkris

Hi, thank you for your reply. What is more important is the clock signal, which should also come from SYSTEM GENERATOR. But I cannot get it from SYSTEM GENERATOR. If data coming from SYSTEM GENERATOR is changed at rising edge of external wr_clk, then it maybe have risk of errors, I think.

 

best regards,

YL

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