UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

cancel
Showing results for 
Search instead for 
Did you mean: 
Visitor ldm_as
Visitor
392 Views
Registered: ‎09-04-2019

[SystemVerilog] Cannot assign an unpacked type to a packed type -> how to handle?

Jump to solution

Hi All,

What's wrong with the following code (SystemVerilog):

module A (
input [W-1:0] in,
output [W-1:0] out
);
reg pipe[W-1:0][L-1];
assign out[W-1:0] = pipe[L-1]; // <- error message for this line
genvar i; generate for (i=0; i < L; i=i+1) begin : g_pipe always @ (posedge clk) pipe[i] <= (i=0) ? in : pipe[i-1]; end endgenerate

I'm receiving the following error message in Questa: (vlog-13215) Cannot assign an unpacked type 'reg $[0:L-1-1]' to a packed type 'reg[W-1:0]'

How the above code should be re-writtenso it could be compiled with Questa?

Thank you!

 

0 Kudos
1 Solution

Accepted Solutions
Highlighted
Scholar markcurry
Scholar
289 Views
Registered: ‎09-16-2009

Re: [SystemVerilog] Cannot assign an unpacked type to a packed type -> how to handle?

Jump to solution

One assumes "W", and "L" are parameters... (Hint try and post more complete examples).

Your "pipe" variable is:

reg pipe [ W-1:0][L-1];

(FWIW I find it bizare to mix [MSB:LSB] indices mixed alongside [WIDTH] indices within a single variable. Just asking for trouble..)

The first index into the unpacked  variable "pipe" is the [W-1:0] dimension.

So,

pipe[0] == pipe[0][L-1];
pipe[1] == pipe[1][L-1];

So, a single index into "pipe" returns an item with L bits.  i.e. 

$bits( pipe[ 0 ] ) == L;

Your line in error:

assign out[W-1:0] = pipe[L-1];

You're right hand expression is a SLICE of an exisiting unpacked array - pulling out a range of indicies.

If L <= W the expression would at least be address an set of array indicies where are in bound.

If L > w, then you have and array out of bounds error.

Even if the former, however, SystemVerilog unpacked arrays are more strongly typed.  And your left hand side type doesn't match your right hand side type. This is exactly the error message you are getting from Questa. 

Your for loop below also get's the indexing wrong on the pipe[i] assignments.  Again the first index of "pipe" indexes from 0 to W-1, (but your for loop runs from 0 to L-1)

I suggest reviewing some SystemVerilog packed/unpacked array examples.

Regards,

Mark

View solution in original post

1 Reply
Highlighted
Scholar markcurry
Scholar
290 Views
Registered: ‎09-16-2009

Re: [SystemVerilog] Cannot assign an unpacked type to a packed type -> how to handle?

Jump to solution

One assumes "W", and "L" are parameters... (Hint try and post more complete examples).

Your "pipe" variable is:

reg pipe [ W-1:0][L-1];

(FWIW I find it bizare to mix [MSB:LSB] indices mixed alongside [WIDTH] indices within a single variable. Just asking for trouble..)

The first index into the unpacked  variable "pipe" is the [W-1:0] dimension.

So,

pipe[0] == pipe[0][L-1];
pipe[1] == pipe[1][L-1];

So, a single index into "pipe" returns an item with L bits.  i.e. 

$bits( pipe[ 0 ] ) == L;

Your line in error:

assign out[W-1:0] = pipe[L-1];

You're right hand expression is a SLICE of an exisiting unpacked array - pulling out a range of indicies.

If L <= W the expression would at least be address an set of array indicies where are in bound.

If L > w, then you have and array out of bounds error.

Even if the former, however, SystemVerilog unpacked arrays are more strongly typed.  And your left hand side type doesn't match your right hand side type. This is exactly the error message you are getting from Questa. 

Your for loop below also get's the indexing wrong on the pipe[i] assignments.  Again the first index of "pipe" indexes from 0 to W-1, (but your for loop runs from 0 to L-1)

I suggest reviewing some SystemVerilog packed/unpacked array examples.

Regards,

Mark

View solution in original post