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Visitor ldm_as
Visitor
317 Views
Registered: ‎09-04-2019

[SystemVerilog] generate statement for declarations -> could be used?

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Hi all,

Can I declare a reg/logic using the generate if ... statement?

Here is an example:

generate if (L>0) reg pipe[W-1:0][L-1]; endgenerate
...
generate
if (L==0) assign out[W-1:0] = in[W-1:0];
else assign out[W-1:0] = pipe[L-1]; // <- error message for this line
endgenerate

Here 'L' is a parameter, which is passed to the module. The 'L' value could be '0' as well.

While compiling the design with Questa, I'm receiving the following message: "Undefined variable: 'pipe'";

So, what's wrong? Why the generate statement cannot be used for declarations? Could be? How?

Thank you 

 

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Scholar markcurry
Scholar
209 Views
Registered: ‎09-16-2009

Re: [SystemVerilog] generate statement for declarations -> could be used?

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Variables declared within a generate scope are local to that generate scope.

So, yes you can declare the register "pipe", as you've shown.  However you cannot access the register "pipe" from outside that generate scope.

If you need variables from within a modules entire scope, then you must declare those variables within the full module scope.

In your example, just handle the "out" assignment from within the same generate loop:

generate
if (L>0) 
begin : L_non_zero
  reg pipe[W-1:0][L-1]; 
  assign out[W-1:0] = pipe[L-1]; 
  // Note your indexing of pipe is wrong too - see the other thread...
end
else 
begin : L_zero
  assign out = in;
end
endgenerate

Regards,

Mark 

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1 Reply
Highlighted
Scholar markcurry
Scholar
210 Views
Registered: ‎09-16-2009

Re: [SystemVerilog] generate statement for declarations -> could be used?

Jump to solution

Variables declared within a generate scope are local to that generate scope.

So, yes you can declare the register "pipe", as you've shown.  However you cannot access the register "pipe" from outside that generate scope.

If you need variables from within a modules entire scope, then you must declare those variables within the full module scope.

In your example, just handle the "out" assignment from within the same generate loop:

generate
if (L>0) 
begin : L_non_zero
  reg pipe[W-1:0][L-1]; 
  assign out[W-1:0] = pipe[L-1]; 
  // Note your indexing of pipe is wrong too - see the other thread...
end
else 
begin : L_zero
  assign out = in;
end
endgenerate

Regards,

Mark 

View solution in original post