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Adventurer
Adventurer
1,522 Views
Registered: ‎11-08-2017

[VHDL] procedure -> can be concurrent assignments?

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Hi All,

 

As for the procedures in VHDL, can they operate as concurrent assignments?

 

Let's say I need to write the following concurrent assignments for the signals:

a<= b;

c<=d;

 

So, can I write a procedure for this assignments and then call it from the entity architecture?

 

Example for the procedure:

procedure PROC (a : in   std_logic, b : in   std_logic,
                              c : out std_logic, d : out std_logic)
begin 
   c := a;
   d := b; 
end

 

Example the procedure call: 

architecture ABC of ABC is 
  signal a,b,c,d : std_logic;
begin
  PROC(a,b,c,d);
end

In the above example, will the signals be continuously assigned? Will any change in the signals a and b be seen in the signals c and d? Is this synthesizable?

 

If that is, so what the difference between a procedure and some entity with the same logic instance?

 

Thank you!

 

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Explorer
Explorer
2,196 Views
Registered: ‎09-07-2011

Re: [VHDL] procedure -> can be concurrent assignments?

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In general, you have to pass them as parameters.   An exception is if a procedure is declared in a process - however then it  cannot be called concurrently.    

 

There's a lot of detail in this language...    check out "The Designers Guide to VHDL"  by Ashenden.

 

Lot of these details are covered with examples.

View solution in original post

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3 Replies
Explorer
Explorer
1,501 Views
Registered: ‎09-07-2011

Re: [VHDL] procedure -> can be concurrent assignments?

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Yes - however you would to use "signals" on the procedure interface -  You can google lots of examples.

 

 

An entity with only one process could be modelled as a procedure. 

 

Should be perfectly synthesizable - however I'd try it out with Vivado.     

Adventurer
Adventurer
1,497 Views
Registered: ‎11-08-2017

Re: [VHDL] procedure -> can be concurrent assignments?

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Are the ports of the current hierarchy (where the procedure is called from) visible to the procedure?

 

So, if I want to use the ports inside of the procedure, should I not need to pass them to there as parameters?  

 

Thanks :-)

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Explorer
Explorer
2,197 Views
Registered: ‎09-07-2011

Re: [VHDL] procedure -> can be concurrent assignments?

Jump to solution

In general, you have to pass them as parameters.   An exception is if a procedure is declared in a process - however then it  cannot be called concurrently.    

 

There's a lot of detail in this language...    check out "The Designers Guide to VHDL"  by Ashenden.

 

Lot of these details are covered with examples.

View solution in original post

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