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Adventurer
Adventurer
101 Views
Registered: ‎09-14-2018

Vivado 12-3563 error (MIG-7 DDR3)

Hello,

I tried to re-generate MIG-7 DDR3 with different clock frequency (Vivado 2018.3, Kintex-7). I got a message (attached) stating that the Nested sub-design can only be generated by its parent sub-design.

I was able to make several copies of the project with different DDR3 clock values before. Never seen that message. I am wondering why it happens this time?

Thank you.

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1 Reply
Adventurer
Adventurer
67 Views
Registered: ‎09-14-2018

Re: Vivado 12-3563 error (MIG-7 DDR3)

It turns out that in this copy of the project after MIG-7 IP update Vivado automatically generated output products, which did not happen before.

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