Vivado is synthesizing Simulation code style into hardware?
This morning I accidentally forget in my top a test if-else of kind module.internal_signal like, e.g.,
Signal = 1'b1
Signal = 1'b0
And both synthesis and implementation passed. Is this allowed?
In addition to that a piece of code I was testing a piece of initial block was there and also seems Vivado accepted and synthesized and implemented it.
Is this expected to be allowed? Or did I missed anything in my configuration to, as expected, the synthesis already flag this as mistake and thrown an error? Is this an issue or I am being too 'old school'?