10-06-2020 05:28 PM - edited 10-07-2020 04:08 AM
Hello, I'm working to get a Partial Reconfiguration flow in a design with mixed RTL Source/IPI Diagram involving a MIG with Vivado 2018.3. The module I am trying to partially reconfigure is not within a block diagram and I have followed the steps in UG909 for a "Software Flow" which uses non-project mode bottom-up OOC synthesis. Without actually adding the commands to enable PR, and just building a single static bottom-up design, I am unable to get MIG in the static design to initialize. In our previous project-mode flow, the MIG works and initializes fine.
My guess is that when using a top-level synthesized .dcp file that includes a static MIG in a PR flow (and since it only reads in the .dcp files for implementation), some constraints and IP data within the .xci of the original synthesis run is not being used in the implementation flow. If this is true, is there a way for the bottom-up non-project mode "Software Flow" for PR to ever work when a design involves complex Xilinx IP such as the MIG? Would using the Project Flow be the way to move forward in our case?
Thanks for any help!
10-07-2020 05:26 AM - edited 10-07-2020 06:42 AM
I'm thinking my problem could be the .elf not being associated as described in: https://www.xilinx.com/support/answers/64923.html
Can this issue be avoided if the MIG is pulled out of the Block Diagram or if the Block diagram is generated OOC by IP instead of global? OOC by IP would require adding each IP's .dcp file to the implementation flow which isn't attractive, but would this allow for the .elfs and .bmms to be associated automatically? Should I be having to manually associate these files in Vivado 2018.3?
10-15-2020 03:17 PM
If the ELF data is not populating in the current design, I would try using the SCOPED_TO_CELLS and SCOPED_TO_REF properties as suggested in the following AR.
10-20-2020 05:23 AM
Thanks for the reply, I was able to get the MIG to initialize by associating the MIG's Microblaze's .elf and .bmm files as stated above.
I did this by adding the SCOPE_TO_REF/SCOPE_TO_CELLS tcl commands after the synthesis run and then generating a checkpoint. This synthesized checkpoint carried the memory intialization through the rest of the PR flow.