08-07-2018 07:56 AM
I utilized Xilinx's partial reconfig demo (with the shift reg and counter) and ported those concepts over to my own design. I can successfully create bit files for my project...but I have some critical warnings I'm not sure how to get rid of.
I have 3 xdc files. One is pin assignments, one is for the static portion of the code, and one is for the reconfigurable modules in the code. I use the approach of a top-level TCL script (which is basically just a modified version of the design_complete script that's included in the previously mentioned demo) to build my chip. Looking through the log file after the build, in conjunction with the command log, I believe I know what's going on, but I don't know how to solve it.
In command.log, as you can imagine, first the script synthesizes the top level modules, then it performs an OOC synthesis for the RPs and associated RMs. I have 2 RPs with 2 RMs each, so synth_design is run a total of 5 times (static, RP1RM1, RP1RM2, RP2RM1, RP2RM2). A DCP is written for each of these.
In the vivado log file, I see that after finishing synthesis, it next moves on to implementation. It loads in the top-level (static) DCP, but then loads in all of my constraint files. Because only the static DCP has been loaded at this point, it issues critical warnings for all of the constraints found in the XDC for the RPs. According to the command log, only after adding in all the XDCs does it then add the DCPs for the RPs. In other words - it's loading and parsing constraints for the RPs before the DCPs for those RPs are even loaded into memory.
I believe that ultimately the constraints are processed correctly, because I meet all my timing when I examine the timing summary report. But what can I do to avoid all these warnings? Again, I'm utilizing the scripting that was included in the demo...in that script (design_complete.tcl), they point to a single directory that has all the xdc files, and those xdc files are all loaded at once when the script gets to the implementation stage.
Any thoughts? TIA...
08-07-2018 08:17 AM
08-07-2018 08:42 AM
OK, I'll check into that...but why would the scripts from Xilinx default to parsing all the XDCs before loading in the associated DCPs?
08-07-2018 11:42 AM
Digging into this some more, I don't think all of my constraints are being used like I thought they were...
Can anyone offer any advice on where I can find more info about this statement from the tutorial:
This top-level XDC file should only contain constraints that reference objects in the static design. Constraints for logic or nets inside of the RP can be applied for specific Reconfigurable Modules if needed.
How do I apply the constraints to a "specific RM" ??
08-07-2018 06:14 PM
OK, I think I figured this out...this answer is somewhat specific to the tutorial flow, but the concepts would apply to any custom flow as well.
The scripts from Xilinx support several module attributes that are used during implementation. The only one shown in the tutorial is called implXDC, which results in the add_file command being issued to add in the XDCs alongside the synthesis DCP before adding in the RP DCPs and linking the design, as I described previously.
If instead I use the linkXDC attribute, then the read_xdc command (instead of add_file) is used, and it's issued *after* the synthesis and respective RP DCPs are added, and therefore the constraints within the XDC are interpreted properly.
There are several other attributes as I mentioned...you can start by looking at the design_utils.tcl script included in the tutorial.