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orangepeace
Explorer
Explorer
6,991 Views
Registered: ‎11-02-2011

during the partial bit file configuration, what happens?

Hi All,

 

   My design is below:

   Part: Virtex-6

   Tool: PlanAhead with Partial Reconfiguration

    There are two reconfigurable partitions in my design RP1 and RP2. Each RP contains two reconfigurable modules.

   That's to say RP1 : RM1a, RM1b;   RP2: RM2a, RM2b  

  I create two configurations: 

    config_1: static logic + RM1a + RM2a

    config_2 : static logic + RM1b + RM2b

 

  if  I configurate the FPGA with config_1.bit,RM1a.bit, RM2a.bit.  Then I configurate RP1 with RM1b.bit, during this configuration, what's the output of the RP1? Does it still keep the circuit of RM1a?

 

Thanks

Best Regards

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woodsd
Xilinx Employee
Xilinx Employee
6,983 Views
Registered: ‎04-16-2008

Please read the PR User Guide:

http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_7/ug702.pdf

 

There is a section on decoupling logic that explains that the RP outputs wll be unknown (potentially toggling) during the PR process. You may need to decouple these outputs from Static.

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