06-17-2013 05:06 AM
I am using virtex-5 FX30T fpga, i wrote, and simulated a code that generates triangular and sawtooth signals (8 output bits), and i need to output these bits to appropriate pins to connect them to a DAC (digital to analog converter). I looked at all relevant datasheets. This (http://www.files.em.avnet.com/files/177/xlx_v5fxt_evl-ug-rev1.pdf) is the datasheet for the fpga, the xilinx user guide for fpga's (http://www-inst.eecs.berkeley.edu/~cs150/sp13/resources/ug190.pdf) makes it seem that i should use OBUF outputs (chapter 6), and the virtex 5 gpfa packaging and pinout (http://www.xilinx.com/support/documentation/user_guides/ug195.pdf) doesn't seem to offer any clear indications as to what pins are OBUF(my device is the one corresponding to the table starting at page 40 (FF665)).
How can i know to what pins should i map my outputs in the ucf constraints file in order to able to output the bits of my signal and then use them to drive a digital-to-analog cicuit (such as a R-2R ladder)?
06-17-2013 07:17 AM
Almost ALL IO pins can be configured as OBUF...
Any IO pin that can output, will output, if it is instantiated as an OBUF.
One post, on one forum is sufficient, do not multiple post the same question. OK? I see all posts, and so do many others.
06-18-2013 05:12 AM
Thank you for your help. I just wanted to check if i could use (for example) DDR2 pins to output the bits, but using the virtex-5 datasheets i can see the corresponding pin numbers of various pins but i cannot see them on the actual board; on the board i usually see what is known as reference number (for example http://www.files.em.avnet.com/files/177/xlx_v5fxt_evl-ug-rev1.pdf page 15 shows the distinction between reference number and pin number), so are the DDR2 unavaiable in order to use them to drive an external cicuit? If they are, how can i locate them on my board and if not, then what pins could be used and connected to an external circuit (perhaps through a simple wire)?
06-18-2013 07:00 AM
Implies that you are interfacing to DDR2 memories. For that, you have to look at the schematics, and the DDR2 memory interface generator (MIG). There are restrictions of which pins may be used, due to timing, skew, etc. That is why the board is made the way it is, and connected as shown in the schematics. If you are doing your own board, follow the recommendations exactly -- no changes.
And read about the MIG. And read the all the users guides.
06-20-2013 12:47 AM
Thank you for your reply,
I just have a few concerns. I am trying to use the SAM pins (they can be configured as general purpose user I/O pins) as output pins and want to use them to drive an external circuit. I have designed and simulated codes for generating digital signals. I wanted to try and see if i can obtain a voltage across some of these pins ebfore trying to generate signals. I did a very simple example in which i tried setting some output pins as OBUF such that their I/O standard matches the Vcc of their bank (3.3V). But i have not been successful in obtaining a voltage across the pins. Also, even the pins which are in the data sheet set to 3.3 V (http://www.files.em.avnet.com/files/177/xlx_v5fxt_evl-ug-rev1.pdf page 18 pin 1), when i measure the voltage from them to ground i also don't get any reading. Aren't such pins fixed to 3.3V? Any thoughts on how to be able to obtain a voltage? Also, this is the simple code i am using to test the pins:
library IEEE; use IEEE.STD_LOGIC_1164.ALL;
Library UNISIM; use UNISIM.vcomponents.all;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
-- Uncomment the following library declaration if instantiating -- any Xilinx primitives in this code. --library UNISIM; --use UNISIM.VComponents.all;
entity testingsampins is
Port ( clk : in STD_LOGIC; test : out STD_LOGIC);
architecture Behavioral of testingsampins is
signal test1: std_logic;
component OBUF port(I: in STD_LOGIC; O: out STD_LOGIC);
U3 : OBUF port map (I => test1, O => test);
Here is my UCF file:
NET "clk" IOSTANDARD = LVTTL;
NET "test" IOSTANDARD = LVTTL;
NET "test" LOC = F5;
06-20-2013 03:43 AM
problem solved! (i wasn't putting the probes of the multimeter on the base of the pins, i was putting it at their tip)
I just want to check is my methodology for obuf instantiation and mapping correct?
07-02-2013 01:40 AM
I didn't want to start a new post because the topic is still under outputting bits... When outputting a 16 bit triangular signal and connecting it to a DAC, i get multiple interfering versions of it, but when using 8 bits it works fine. Could this be due to the 16 bits not being outputted simultaneously?, I instantiated all the output pins as OBUF LVTTL. If they are always outputted simultaneously, any thoughts for the reason behind this behavior?