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Explorer
Explorer
7,108 Views
Registered: ‎11-23-2013

set_property "LOC" in OOC flow doesn't work

Hello, I combined my logic and a PCIe core's .dcp(synth) file in pcie_adapter module. And I want to implement the pcie_adapter module in OOC mode.

I defined the location in *_ooc_phys.xdc file like this:

    set_property LOC BUFGCTRL_X0Y27 [get_cells {pcie_7x_0_support_i/pipe_clock_i/userclk1_i1.usrclk1_i1}]

 

But after implementation, I always get critical warning like this:

    HDOOC-4#1 Critical Warning
No Pblock range or LOC for cell
11 Cells are found with no placement constraints. Failure to control placement of logic with either a Pblock or a LOC constraint may result in placement conflicts if the out-of-context implementation results are reused in a top-level design. The following is a list of cells (up to the first 15) with no placement constraints:
ibuf_sys_n (IBUF)
ibuf_sys_p (IBUF)
ibuf_sys_rst (IBUF)
pcie_7x_0_support_i/pcie_7x_0_i/inst/inst/gt_top_i/pipe_wrapper_i/cpllpd_refclk_inst (BUFG)
.......

 

Attachment is my project. The OOC synth and implement flows are controlled by design_complete.tcl. Other related .tcl files are all come from ug946.

 

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Xilinx Employee
Xilinx Employee
7,091 Views
Registered: ‎09-20-2012

Hi @carnby

 

Is this warning seen during OOC Implementation?

 

Did you see any critical warning saying that the tool was not able to apply the constraint?

 

Thanks,

Deepika.

Thanks,
Deepika.
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Xilinx Employee
Xilinx Employee
7,083 Views
Registered: ‎04-16-2008

It looks like the cell name given in the LOC constraint does not match the cell name given in the message:

 

From Constraint:

pcie_7x_0_support_i/pipe_clock_i/userclk1_i1.usrclk1_i1}

From Critical Warning:

pcie_7x_0_support_i/pcie_7x_0_i/inst/inst/gt_top_i/pipe_wrapper_i/cpllpd_refclk_inst

 

It could be that the LOC did take affect, but that you need an additional LOC on this other BUFG cell. 

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Explorer
Explorer
7,075 Views
Registered: ‎11-23-2013

Hello,

pcie_7x_0_support_i/pcie_7x_0_i/inst/inst/gt_top_i/pipe_wrapper_i/cpllpd_refclk_inst was constrained in the pcie_adapter_inst1_ooc_phys.xdc file, line 19. And another you mentioned was constrained in line 16 like this:

set_property LOC BUFGCTRL_X0Y27 [get_cells {pcie_7x_0_support_i/pipe_clock_i/userclk1_i1.usrclk1_i1}]

 

 

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Explorer
Explorer
7,074 Views
Registered: ‎11-23-2013

Hello, 

Yes, the critical warnings all generated in the OOC flow. 

Attachments is the figure of error message. 

20151106094230.png

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Xilinx Employee
Xilinx Employee
7,035 Views
Registered: ‎04-16-2008

Were you able to find the in the log file where the XDC is being processed?  Did you see any Critical Warnings about these LOC constraints? I've never seen an issue like this.  If the constraint it properly written (has correct hierachical cell name), the LOC should be correctly applied.  Plesse verify that the names are properly scoped to the module level. (ie. /pcie_7x_0_support_i/... and not /toplevel_wrapper/pcie_7x_0_support_i/...).

 

If you still can't get this to work, try to open up the post-opt_design DCP in the GUI, and assign the LOC constraints there. You can drag and drop the BUFG, GT, and IO buffer cells to the location you want them to go. If you can get them assigned in the GUI, then the Tcl Console will contain the XDC constraint used that can then be compared to your current XDC constraints. 

 

 

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