04-25-2019 03:03 AM
[DRC REQP-1884] ODDR_has_invalid_load: ODDR cell ODDR_INST loads should only be an output buffer or a port, but it is driving an invalid load (one or more of): out_OBUF_inst, u_ila_0/inst/ila_core_inst/shifted_data_in_reg_srl8, and u_ila_0/inst/ila_core_inst/u_trig/U_TM/N_DDR_MODE.G_NMU.U_M/allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst/probeDelay1_i_1
04-25-2019 10:43 AM
You can only use ILA's on "internal" FPGA signals. The output of an ODDR cell is a top-level IO, and not able to be probed by an ILA.
04-29-2019 06:30 PM
As said in the message, the ODDR output can only directly drive output port. It cannot drive fabric.
If you want to probe the output signal, you may consider adding ODDR input to ILA probe port.
05-15-2019 11:26 PM
05-16-2019 12:27 AM
Hi, @bharat1992 ,
Does the detailed information of the error message change?
Please confirm the connection bwtween ODDR/Q and ILA is removed.