07-10-2019 08:08 AM
I am using Vivado 2019.1 to generate a bitstream with debug cores. After downloading the bitstream through jtag, I am getting the following error:
WARNING: [Labtools 27-1972] Mismatch between the design programmed into the device xcku115 (JTAG device index = 0) and the probes file(s) admpcie8k5_bringup.ltx.
The core at location uuid_23E7D65A79BC59F7BC47406C1714DFAE has different widths for ILA input port 22. Port width in the device core is 56, but port width in the probes file is 55.
I am using Vivado 2019.1 in Linux (Debian). The way I added debug core is: 1) mark buses as debug in block design, 2) open synthesis result and add debug core then save to constraints, 3) generate bitstream. I have been doing it this way for a long time and works for 2017.2, which is the latest one I used before 2019.1. Any help will be highly appreciated.
07-11-2019 01:25 PM
It's possible that your LTX file has been incorrectly generated for some reason.
Could you please open the synthesized design and run the command:
Make sure to save it with a different name so it doesn't get confused with the existent LTX file.
You can either inspect this file (open with a text editor) and verify if the input port 22 now has a width of 56 nets, or you can go ahead and try to program de device and use this LTX to see if it now works.
Please let us know if that solves the issue.
07-12-2019 06:22 AM
Hi @anunesgu ,
I have tried what you suggested but I do have to run the command after opening the opt_design checkpoint as the debug core is generated in that stage. The two debug probe files look very different to me, xml based vs json based. Please find attached the two probe files, debug_opt.ltx is generated using checkpoint manually, while the other one is the original one. Let me know if there is anything you want me to do.
07-12-2019 10:41 AM
Thanks for sharing the files.
That might be one of the issues. Before Vivado 2018.3, the LTX file was written in XML. For Vivado 2018.3 and newer, it's now JSON formatted.
I wonder why you still had the file in XML format since you are using 2019.1. It might have been that you upgraded the project and that file stayed there from the 2017.2 version.
Have you had the chance to program the FPGA and use the new JSON Bitstream? Did it still show the same issue?
About generating the LTX file, I normally recommend generating with the Synthesized design open (instead of the Implemented one) because at that point, although the core has not been officially created, it already knows the probes and net names that will be connected. In addition, the Implementation process sometimes optimize the design and end up removing/renaming/combining nets, which may also cause the LTX file to be modified and not show the probes the way you wanted.
07-12-2019 11:04 AM
Hi @anunesgu ,
Good catch, I just found that I opened the 2017.2 version checkpiont. My appologies. I have attached the new debug probes file here. So I have tried to do the same thing with the right checkpoint, here is the summary:
1) using the generated debug files with bitstream works, also all the signal names is so much readable. Is there any way to force this version instead of the one automatically generated? The meaningless signal names like "lopt" has been quite a problem for me since 2017.x.
2) I did try to simply open synthesis result as you suggested, but got the following error: Unable to generate LTX file since debug core UUIDs are unavailable for unimplemented cores. Resolution: Issue the write_debug_probes TCL command after opt_design (or implement_debug_core)....
07-16-2019 10:51 AM
1) Vivado will always generate the ltx file automatically after implementation, and if you are using Vivado 2018.3 or newer, it will always be in the JSON format.
The issue with the "lopt" names is an effect of the optimizations going on during the implementation process. In some cases, regenerating the LTX manually creates a valid LTX, but that not always works. The most accepted solution, when the renaming issue happens, is to apply a DONT_TOUCH to the parent nets of the net segments marked for debug and being renamed:
set_property DONT_TOUCH 1 [get_nets [get_property PARENT <net marked for debug> ] ]
2) I believe it depends on what flow you are using to insert the ILA. If you are using the Setup Debug Flow, it should be possible to generate the LTX in the synthesized design. If you are using the HDL instantiation flow, then it might not work until the Implementation is complete.
07-16-2019 11:08 AM
Hi @anunesgu ,
Your answer all makes sense, except that I don't see "lopt" signal names in 2015.x, so there must be a way to solve it in the old tool. Using tcl command is not always possible or it is very troublesome as when I am debugging, I am choosing hundreds of different signals every run. I guess the current solutions that can work for me is to always manually generate the debug.ltx after opt design.
Anyway, this seems to be a bug in 2019.1 regardless of the inreadable signal names, right? There shouldn't be any reason that the auto generated ltx file does not match the implementation.