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10,118 Views
Registered: ‎04-23-2009

Problem during translate (NgdBuild.exe 604) when using Synplify Pro, ISE and NGC files

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I have a problem during 'translate' step of the following design:

 

1/° Tools:

 

     I use Synplicity Synplify Pro 9.6.2 for synthesis and Xilinx ISE 10.1.03[K39] (service pack 3) for place and route.
     Synplify is integrated into ISE.

 

 

 

2/° Design hierarchy:

 

     Here is my design hierarchy:

 

          TI_INTERFACE (entity : work.TI_INTERFACE)
            |
            +---- RST_GENERATION (entity : lib_ti_interface.RST_GENERATION)
            |
            +---- ROUTEUR_INTERFACE (entity : lib_ti_interface.IF_BUS_ROUTEUR)
            |       |
            |       +---- I_GESTION_MEM (entity : ip_routeur_tools.GESTION_MEM)
            |       |
            |       +---- I_MEMOIRE_8PORTS (entity : ip_routeur_tools.MEMOIRE_8PORTS)
            |               |
            |               +---- GEN_PORT_1.INST_MEMOIRE_PORT1 (entity : ip_routeur_tools.MEMOIRE_PORT)
            |               |       |
            |               |       +---- INST_MEMOIRE_PORT1 (entity : xilinx.DP_BRAM_XY)
            |               |
            |               +---- GEN_PORT_2.INST_MEMOIRE_PORT1 (entity : ip_routeur_tools.MEMOIRE_PORT)
            |               |       |
            |               |       +---- INST_MEMOIRE_PORT1 (entity : xilinx.DP_BRAM_XY)
            |               |
            |               +---- GEN_PORT_3.INST_MEMOIRE_PORT1 (entity : ip_routeur_tools.MEMOIRE_PORT)
            |                       |
            |                       +---- INST_MEMOIRE_PORT1 (entity : xilinx.DP_BRAM_XY)
            |
            +---- IP_UDP_RECEIVE (entity : lib_ti_interface.IP_UDP_RECEIVE)
            |       |
            |       +---- MSG_BUFFER (entity : lib_common.RAM_SYNC)
            |
            +---- TI_CONTROL (entity : lib_ti_interface.TI_CONTROL)
            |
            +---- TI_CONTROL_RESYNC (entity : lib_ti_interface.TI_CONTROL_RESYNC)
            |
            +---- VIDEO_TRANSMIT_BUFFER (entity : lib_ti_interface.VIDEO_TRANSMIT_BUFFER)
            |       |
            |       +---- MSG_BUFFER (entity : lib_common.RAM_ASYNC)
            |
            +---- VIDEO_TRANSMIT (entity : lib_ti_interface.VIDEO_TRANSMIT)
            |
            +---- VIDEO_RECEIVE (entity : lib_ti_interface.VIDEO_RECEIVE)
            |
            +---- VIDEO_RECEIVE_BUFFER (entity : lib_ti_interface.MBDA_FIFO_WRAPPER)
            |       |
            |       +---- CORE (entity : lib_ti_interface.FIFO_ASYNC)
            |               |
            |               +---- I_RAM (entity : lib_common.RAM_ASYNC)
            |
            +---- IP_UDP_TRANSMIT (entity : lib_ti_interface.IP_UDP_TRANSMIT)
            |       |
            |       +---- CHECKSUM_CALCULATOR (entity : lib_ti_interface.CHECKSUM_CALCULATOR)
            |
            +---- PLB_INTERFACE (entity : lib_ti_interface.PLB_INTERFACE)
                    |
                    +---- IPIF_CONTROLLER (entity : lib_ti_interface.IPIF_CONTROLLER)
                    |
                    +---- IPIF_RESYNC (entity : lib_ti_interface.IPIF_RESYNC)
                    |
                    +---- PLB_IPIF_BRIDGE (entity : PLB2IPIC)

      
      
      
3/° VHDL Modules:

 

     The following modules are described in VHDL and synthetised into different libraries :
      
          xilinx.DP_BRAM_XY

          ip_routeur_tools.GESTION_MEM
          ip_routeur_tools.MEMOIRE_8PORTS
          ip_routeur_tools.MEMOIRE_PORT

          lib_common.RAM_ASYNC
          lib_common.RAM_SYNC

          lib_ti_interface.CHECKSUM_CALCULATOR
          lib_ti_interface.FIFO_ASYNC
          lib_ti_interface.IPIF_CONTROLLER
          lib_ti_interface.IPIF_RESYNC
          lib_ti_interface.IP_UDP_RECEIVE
          lib_ti_interface.IP_UDP_TRANSMIT
          lib_ti_interface.MBDA_FIFO_WRAPPER
          lib_ti_interface.PLB_INTERFACE
          lib_ti_interface.IF_BUS_ROUTEUR
          lib_ti_interface.RST_GENERATION
          lib_ti_interface.TI_CONTROL
          lib_ti_interface.TI_CONTROL_RESYNC
          lib_ti_interface.VIDEO_RECEIVE
          lib_ti_interface.VIDEO_TRANSMIT
          lib_ti_interface.VIDEO_TRANSMIT_BUFFER

          work.TI_INTERFACE
      
  
      
4/° 'PLB_IPIF_BRIDGE' module:

 

     PLB_IPIF_BRIDGE is an instance of the module PLB2IPIC.
     This module is provided by a netlist (NGC file).
     In order for implementation to work, we specify the directory in which the NGC file is located in translate options so that Ngdbuild.exe find the netlist.

 

 

 

5/° Synthesis:

 

     Synplify synthetizes all the submodules and the top-level module TI_INTERFACE except module PLB2IPIC which netlist is already available.
     PLB2IPIC is considered as a black-box.
     Result is ti_interface.edn, a netlist in EDIF format.
     Hierarchy is kept.
  

 


6/° ti_interface.edn extract:

 

     I grepped for patterns '(library ' and '(cell ' into the EDIF:
 
  ~/synthesis> grep -e '(library ' -e '(cell ' ti_interface.edn
       (library VIRTEX
         (cell RAMB16 (cellType GENERIC)
         (cell SRL16 (cellType GENERIC)
         (cell IBUF (cellType GENERIC)
         (cell OBUF (cellType GENERIC)
         (cell LUT4_L (cellType GENERIC)
         (cell LUT4 (cellType GENERIC)
         (cell LUT3_L (cellType GENERIC)
         (cell LUT3 (cellType GENERIC)
         (cell LUT2_L (cellType GENERIC)
         (cell LUT2 (cellType GENERIC)
         (cell LUT1_L (cellType GENERIC)
         (cell LUT1 (cellType GENERIC)
         (cell MULT_AND (cellType GENERIC)
         (cell XORCY (cellType GENERIC)
         (cell MUXCY_L (cellType GENERIC)
         (cell MUXCY (cellType GENERIC)
         (cell MUXF6 (cellType GENERIC)
         (cell MUXF5 (cellType GENERIC)
         (cell BUFGP (cellType GENERIC)
         (cell BUFG (cellType GENERIC)
       (library UNILIB
         (cell FD (cellType GENERIC)
         (cell FDP (cellType GENERIC)
         (cell FDC_1 (cellType GENERIC)
         (cell FDC (cellType GENERIC)
         (cell FDPE (cellType GENERIC)
         (cell FDCE (cellType GENERIC)
         (cell INV (cellType GENERIC)
         (cell GND (cellType GENERIC)
         (cell VCC (cellType GENERIC)
       (library lib_common
         (cell ram_asyncZ1 (cellType GENERIC)
         (cell ram_asyncZ0 (cellType GENERIC)
         (cell ram_sync (cellType GENERIC)
       (library xilinx
         (cell dp_bram_xy_2 (cellType GENERIC)
         (cell dp_bram_xy_1 (cellType GENERIC)
         (cell dp_bram_xy (cellType GENERIC)
       (library ip_routeur_tools
         (cell (rename memoire_port_i_memoire_8ports_gen_port_1_inst_memoire_port1_2 "memoire_port_i_memoire_8ports_gen_port_1.inst_memoire_port1_2") (cellType GENERIC)
         (cell (rename memoire_port_i_memoire_8ports_gen_port_1_inst_memoire_port1_1 "memoire_port_i_memoire_8ports_gen_port_1.inst_memoire_port1_1") (cellType GENERIC)
         (cell (rename memoire_port_i_memoire_8ports_gen_port_1_inst_memoire_port1 "memoire_port_i_memoire_8ports_gen_port_1.inst_memoire_port1") (cellType GENERIC)
         (cell gestion_mem (cellType GENERIC)
         (cell memoire_8ports (cellType GENERIC)
       (library lib_ti_interface
         (cell ipif_controller (cellType GENERIC)
         (cell ipif_resync (cellType GENERIC)
         (cell plb2ipic_work_ti_interface_rtl_0 (cellType GENERIC)
         (cell checksum_calculator (cellType GENERIC)
         (cell fifo_async (cellType GENERIC)
         (cell plb_interface (cellType GENERIC)
         (cell ip_udp_transmit (cellType GENERIC)
         (cell mbda_fifo_wrapper (cellType GENERIC)
         (cell video_receive (cellType GENERIC)
         (cell ti_control_resync (cellType GENERIC)
         (cell ti_control (cellType GENERIC)
         (cell video_transmit (cellType GENERIC)
         (cell video_transmit_buffer (cellType GENERIC)
         (cell ip_udp_receive (cellType GENERIC)
         (cell if_bus_routeur (cellType GENERIC)
         (cell rst_generation (cellType GENERIC)
       (library work
         (cell ti_interface (cellType GENERIC)

 

     We can see that each instance of the design produces a cell into the EDIF file.
     Cell name is based on entity name and not on instance name (except for memoire_port instances because there are some 'generate' statements,

     but I have no issue with this).
  

 


7/° My problem

 

     We can see into the EDIF file that the module PLB2IPIC has been handled as a black-box and has produced a cell called 'plb2ipic_work_ti_interface_rtl_0'
 
     Translation does not work because Ngdbuild.exe tries to find the netlist of a module called 'plb2ipic_work_ti_interface_rtl_0'.
     Our NGC file is the netlist of a module called 'plb2ipic'.

     I get the following error:

 

          ERROR:NgdBuild:604 - logical block 'plb_interface/plb_ipic_bridge' with type 'plb2ipic_work_ti_interface_rtl_0' could not be resolved.

                         A pin name misspelling can cause this, a missing edif or ngc file, or the misspelling of a type name.

                         Symbol 'plb2ipic_work_ti_interface_rtl_0' is not supported in target 'virtex4'.


  
     So the problem is this black-box name 'plb2ipic_work_ti_interface_rtl_0' in the EDIF file generated by Synplify during synthesis.
 
     When I modify the EDIF file manually after synthesis and replace 'plb2ipic_work_ti_interface_rtl_0' by 'plb2ipic', then translation works fine, and implementations goes on.
  
     Has anyone faced that problem already?
     Could somebody provide a solution for that?
 

     Thanks a lot.

 

 

  
     Julien

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1 Solution

Accepted Solutions
11,902 Views
Registered: ‎04-23-2009

Re: Problem during translate (NgdBuild.exe 604) when using Synplify Pro, ISE and NGC files

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It turned out this specific problems only happens with Synplify 9.6.2

I returned to Synplify 9.4 and it works fine

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4 Replies
11,903 Views
Registered: ‎04-23-2009

Re: Problem during translate (NgdBuild.exe 604) when using Synplify Pro, ISE and NGC files

Jump to solution

It turned out this specific problems only happens with Synplify 9.6.2

I returned to Synplify 9.4 and it works fine

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Highlighted
8,927 Views
Registered: ‎04-23-2009

Re: Problem during translate (NgdBuild.exe 604) when using Synplify Pro, ISE and NGC files

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OMG !
I changed my machine so I reinstalled my tools and now I am getting this error again...
Still ISE 10.1.03 (nt) K.39 and Synplify Pro 9.4
So is there a way to tell Synplify to look for the original balck-box name ?

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Newbie cgiard
Newbie
8,807 Views
Registered: ‎01-13-2010

Re: Problem during translate (NgdBuild.exe 604) when using Synplify Pro, ISE and NGC files

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I have the same problem.  I use Synplify Pro C-2009.06-SP1 and ISE 11.4.  When I synthetise my project, Synplify change the black box "mig_33" for "mig_33_work_luke_e_luke_a_0".  The webcase 912701 in synopsys data base explain that happen when the black box contain generic, synplify give a different name to every instance of the black box with a different set of generic.  It is too much work to remove all generic from mig because there is a lot of relation between generics and IO.  I tried to remove generic from "Virtex-6 Integrated Block for PCI Express" (because it's easier) and it work.  Synplify doesn't change black box name anymore.

 

The problem is that I don't want to remove generic from black boxes.  Can someone tell me if there is a way disable Synplify from changing name of black boxes with generic?

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Newbie wk2006
Newbie
5,138 Views
Registered: ‎12-07-2013

Re: Problem during translate (NgdBuild.exe 604) when using Synplify Pro, ISE and NGC files

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It wasn't modify instance name, when I use older synplify_pro version (2011-03).

 

If there are anyone who know diable option. please reply.

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