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Visitor kensamuelson
Visitor
7,448 Views
Registered: ‎08-31-2016

Problem with simple IP Creation - Module Reference not supported in this release

Hello,

 

This is a newbie question I'm sure. I'm trying to learn the IP packager and haven't found a good tutorial on it.  So I'm trying it on my own. Here is what I did:

 

I built a small and program with an AND gate. I'm using VHDL.

I build a testbench and verified it. 

I then tried to use Create IP.  It told me that I needed a block diagram to package a block design and later I learned that I needed input and output ports on my design to move forward.

I opened Create IP, Selected Block Design selected xci files (of which there are none since I didn't create it and don't know what they are), selected the repo directory, and hit finish.   

I got the error Module Reference <....>  not supported in this release.  See picture.  It then closed without any other information.

I looked up the error ip-flow 19-4639 on the forum and google and didn't find anything.  Is there a location for what error messages mean or further explanation?

 

Incidentally I did go through the tutorial in UG1119 Creating, Packaging Custom IP Tutorial but this was not helpful because all the files were provided and steps coordinated so you wouldn't get any errors.  I didn't learn very much.    It would be better if I had typed them in myself so I could see what each step meant. 

 

Any suggestion or references to other simple IP creation tutorials would be very helpful.  I can include code or other pictures if needed.

IP_PackageError.jpg
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9 Replies
Xilinx Employee
Xilinx Employee
7,441 Views
Registered: ‎08-01-2008

Re: Problem with simple IP Creation - Module Reference not supported in this release


you can find some examples here
http://www.xilinx.com/support/university/vivado/vivado-teaching-material/digital-design.html
http://www.xilinx.com/support/documentation/university/Vivado-Teaching/Digital-Design/2014x/docs-pdf/Vivado_tutorial.pdf
check this post
https://forums.xilinx.com/t5/Design-Entry/Packaging-custom-IP-with-block-designs/td-p/558247

Thanks and Regards
Balkrishan
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Moderator
Moderator
7,433 Views
Registered: ‎07-21-2014

Re: Problem with simple IP Creation - Module Reference not supported in this release

@kensamuelson

 

If your intention is to create a simple(non-BD) IP then you can simply create a project -> add the RTL files -> verify it -> package it. Done!!

In case of BD, if you are looking for a way to package a BD which includes custom IP: create a small project(temporary project) add your RTL files and package it -> Add the packaged IP in your block design(main project). This will help you to package your design without any issues.

 

Thanks,
Anusheel
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Visitor kensamuelson
Visitor
7,414 Views
Registered: ‎08-31-2016

Re: Problem with simple IP Creation - Module Reference not supported in this release

Thank you for these tutorials they are quite good and very descriptive.  I didn't look at them previously because I have the Arty board and an AC701, not the nexys or basys.  These tutorials didn't come up when looking for tutorials for the Arty board. 

 

I would suggest updating the tutorial for Arty or making a separate one.  These would have saved me considerable time a few weeks ago.    

 

I did follow the instructions and was able to modify the code to work on Arty.  i was also able to create the IP in the tutorial.  The only difference I saw in what the tutorial did and what I did was I used create port rather than make external.  I'm not sure what the specific difference are, I have not investigated further.   

 

When i went back to the project that gave me the original error and changed the ports using "make external" it still would not build. However when I created a brand new project and imported  the VHDL and only used "Make External" the package built perfectly. Can you provide insight or a document that tells me the difference between "Create Ports" and "Make External".

 

Other than that, thank you for the help and tutorials. 

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Visitor kensamuelson
Visitor
7,412 Views
Registered: ‎08-31-2016

Re: Problem with simple IP Creation - Module Reference not supported in this release

Yea,  that's what I thought should happen but I was surprised when it didn't .  See the other reply that I posted. It seemed to have something to do with the "Make External" Ports or the fact that I am using a cut down web version of Vivado supplied with the Arty board. 

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Moderator
Moderator
7,364 Views
Registered: ‎07-01-2015

Re: Problem with simple IP Creation - Module Reference not supported in this release

Hi @kensamuelson,

 

Can you please try creating a top level wrapper over BD and package the current project?

Thanks,
Arpan
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Participant baf2099
Participant
5,171 Views
Registered: ‎03-17-2017

Re: Problem with simple IP Creation - Module Reference not supported in this release

@kensamuelson I'm experiencing the same original issue you had, now in Vivado 2016.4. Is/Was the conclusion that using RTL reference module inside of a block design and then trying to package is simply impossible?

 

Seems crazy to have to separately package every single little RTL module one might need between blocks.

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Moderator
Moderator
5,154 Views
Registered: ‎07-21-2014

Re: Problem with simple IP Creation - Module Reference not supported in this release

@baf2099

 

>>Is/Was the conclusion that using RTL reference module inside of a block design and then trying to package is simply impossible?

Yes, currently this feature is not supported if you packaging the block design.

 

If the "Add Module" is required between two IPs then you will need to package it, else you can try to push it out side of the BD and instantiate in the wrapper.

 

Thanks,
Anusheel
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Participant baf2099
Participant
5,146 Views
Registered: ‎03-17-2017

Re: Problem with simple IP Creation - Module Reference not supported in this release

@anusheel thank you for the clear response! Does anyone know, or can Xilinx comment on if the ability to do this is in the works? If so, any idea what release it could be staged for? 

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Xilinx Employee
Xilinx Employee
2,206 Views
Registered: ‎07-22-2008

Re: Problem with simple IP Creation - Module Reference not supported in this release

Yes, this should be available in Vivado 2018.1.  i just ran a test case and my BD packaged fine with an RTL module in a recent internal build.

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